threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
106 lines
3.3 KiB
C
106 lines
3.3 KiB
C
/*
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* Copyright (C) 2015 MediaTek Inc.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "mu3d_hal_osal.h"
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#include "mu3d_hal_phy.h"
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#include "mu3d_hal_usb_drv.h"
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#include "mtk-phy.h"
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/**
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* mu3d_hal_phy_scan - u3 phy clock phase scan
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*
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*/
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int mu3d_hal_phy_scan(int latch_val, unsigned char driving)
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{
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#ifdef CONFIG_U3_PHY_GPIO_SUPPORT
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int count, fset_phase_val, recov_cnt, link_error_count, U0_count;
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unsigned char phase_val;
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/* unsigned char driving; */
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/* disable ip power down,disable U2/U3 ip power down. */
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mu3d_hal_ssusb_en();
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/* mu3d_hal_pdn_dis(); */
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u3phy_ops->change_pipe_phase(u3phy, 0, 0);
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os_writel(U3D_PIPE_LATCH_SELECT, latch_val); /* set tx/rx latch sel */
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/* driving = 2; */
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u3phy_ops->change_pipe_phase(u3phy, driving, 0);
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phase_val = 0;
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count = 0;
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fset_phase_val = TRUE;
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while (TRUE) {
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if (fset_phase_val) {
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u3phy_ops->change_pipe_phase(u3phy, driving, phase_val);
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mu3d_hal_rst_dev();
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os_ms_delay(50);
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os_writel(U3D_USB3_CONFIG, USB3_EN);
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os_writel(U3D_PIPE_LATCH_SELECT, latch_val); /* set tx/rx latch sel */
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fset_phase_val = FALSE;
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U0_count = 0;
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link_error_count = 0;
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recov_cnt = 0;
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count = 0;
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}
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os_ms_delay(50);
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count++;
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recov_cnt = os_readl(U3D_RECOVERY_COUNT); /* read U0 recovery count */
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link_error_count = os_readl(U3D_LINK_ERR_COUNT); /* read link error count */
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if ((os_readl(U3D_LINK_STATE_MACHINE) & LTSSM) == STATE_U0_STATE) { /* enter U0 state */
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U0_count++;
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}
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if (U0_count > ENTER_U0_TH) { /* link up */
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os_ms_delay(1000); /* 1s */
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recov_cnt = os_readl(U3D_RECOVERY_COUNT);
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link_error_count = os_readl(U3D_LINK_ERR_COUNT);
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os_writel(U3D_RECOVERY_COUNT, CLR_RECOV_CNT); /* clear recovery count */
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os_writel(U3D_LINK_ERR_COUNT, CLR_LINK_ERR_CNT); /* clear link error count */
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pr_debug("[PASS] Link Error Count=%d, Recovery Count=%d\n",
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link_error_count, recov_cnt);
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pr_debug("I2C(0x%02x) : [0x%02x], I2C(0x%02x) : [0x%02x]\n",
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U3_PHY_I2C_PCLK_DRV_REG,
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_U3Read_Reg(U3_PHY_I2C_PCLK_DRV_REG),
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U3_PHY_I2C_PCLK_PHASE_REG,
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_U3Read_Reg(U3_PHY_I2C_PCLK_PHASE_REG));
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pr_debug("Reg(0x130) : [0x%02x], PhaseDelay[0x%02x], Driving[0x%02x], Latch[0x%02x]\n",
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os_readl(U3D_PIPE_LATCH_SELECT), phase_val, driving, latch_val);
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phase_val++;
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fset_phase_val = TRUE;
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} else if ((os_readl(U3D_LINK_STATE_MACHINE) & LTSSM) == STATE_DISABLE) { /* link fail */
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pr_debug("[FAIL] STATE_DISABLE, PhaseDelay[0x%02x]\n", phase_val);
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phase_val++;
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fset_phase_val = TRUE;
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} else if (count > MAX_TIMEOUT_COUNT) { /* link timeout */
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pr_debug("[FAIL] TIMEOUT, PhaseDelay[0x%02x]\n", phase_val);
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phase_val++;
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fset_phase_val = TRUE;
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}
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if (phase_val > MAX_PHASE_RANGE) {
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/* reset device */
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mu3d_hal_rst_dev();
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os_ms_delay(50);
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/* disable ip power down,disable U2/U3 ip power down. */
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mu3d_hal_ssusb_en();
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/* mu3d_hal_pdn_dis(); */
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os_ms_delay(10);
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break;
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}
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}
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#endif
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return 0;
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}
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