threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
293 lines
7.8 KiB
C
293 lines
7.8 KiB
C
/*
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* Copyright (C) 2015 MediaTek Inc.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef USB_HW_H
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#define USB_HW_H
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#include <linux/types.h>
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#define SW_VERSION "20130627"
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/* U3D configuration */
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/*This define for DVT OTG testing*/
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#ifdef CONFIG_USBIF_COMPLIANCE
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#define SUPPORT_OTG
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#endif
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/* This should be defined if superspeed is supported */
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#define SUPPORT_U3
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#ifdef SUPPORT_U3
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#define U3D_DFT_SPEED SSUSB_SPEED_SUPER
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#define U2_U3_SWITCH
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/* #define U2_U3_SWITCH_AUTO */
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#else
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#define U3D_DFT_SPEED SSUSB_SPEED_HIGH
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#endif
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#ifndef CONFIG_USB_MU3D_DRV
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#define POWER_SAVING_MODE
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#endif
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/* clock setting
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* this setting is applied ONLY for DR FPGA
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* please check integrator for your platform setting
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*/
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/* OSC 125MHz/2 = 62.5MHz, ceil(62.5) = 63 */
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#define U3D_MAC_SYS_CK 63
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/* OSC 20Mhz/2 = 10MHz */
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/* #define U3D_MAC_REF_CK 10 */
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#define U3D_MAC_REF_CK 26
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/* U3D_PHY_REF_CK = U3D_MAC_REF_CK on ASIC */
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/* On FPGA, these two clocks are separated */
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#define U3D_PHY_REF_CK 26
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#define PIO_MODE 1
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#define DMA_MODE 2
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#define QMU_MODE 3
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#define BUS_MODE PIO_MODE
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#ifdef CONFIG_USBIF_COMPLIANCE
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#define EP0_BUS_MODE DMA_MODE
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#else
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#define EP0_BUS_MODE PIO_MODE
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#endif
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#define AUTOSET
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#define AUTOCLEAR
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#define BOUNDARY_4K
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#define DIS_ZLP_CHECK_CRC32 /* disable check crc32 in zlp */
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#define CS_12B 1
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#define CS_16B 2
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#if defined(CONFIG_MTK_MD_DIRECT_TETHERING_SUPPORT)
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#define CHECKSUM_TYPE CS_12B
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#else
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#define CHECKSUM_TYPE CS_16B
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#endif
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#define U3D_COMMAND_TIMER 10
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#if (CHECKSUM_TYPE == CS_16B)
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#define CHECKSUM_LENGTH 16
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#else
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#define CHECKSUM_LENGTH 12
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#endif
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#define NO_ZLP 0
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#define HW_MODE 1
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#define GPD_MODE 2
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#ifdef _USB_NORMAL_
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#define TXZLP NO_ZLP
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#else
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#define TXZLP GPD_MODE
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#endif
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#define ISO_UPDATE_TEST 0
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#define ISO_UPDATE_MODE 1
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#define LPM_STRESS 0
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/* USBIF , uevent */
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/* #define USBIF_OTG_EVENT_DEV_CONN_TMOUT "DEV_CONN_TMOUT" */
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/* #define USBIF_OTG_EVENT_NO_RESP_FOR_HNP_ENABLE "NO_RESP_FOR_HNP_ENABLE" */
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/* #define USBIF_OTG_EVENT_HUB_NOT_SUPPORTED "HUB_NOT_SUPPORTED" */
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/* #define USBIF_OTG_EVENT_DEV_NOT_SUPPORTED "DEV_NOT_SUPPORTED" */
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#define USBIF_OTG_EVENT_HNP_FAILED "HNP_FAILED"
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#define USBIF_OTG_EVENT_NO_RESP_FOR_SRP "NO_RESP_FOR_SRP"
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/*EP number is hard code, not read from U3D_CAP_EPINFO*/
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#define HARDCODE_EP
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extern void __iomem *u3_base;
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extern void __iomem *u3_ippc_base;
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#ifdef CONFIG_FPGA_EARLY_PORTING
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extern void __iomem *i2c_base;
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extern u32 i2c_physical_base;
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#endif
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/**
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* @U3D register map
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*/
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/*
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* 0x1127_0000 for MAC register
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*/
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/* 4K for each, offset may differ from project to project. Please check integrator */
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#define SSUSB_DEV_BASE (u3_base+0x1000)
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#define SSUSB_EPCTL_CSR_BASE (u3_base+0x1800)
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#define SSUSB_USB3_MAC_CSR_BASE (u3_base+0x2400)
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#define SSUSB_USB3_SYS_CSR_BASE (u3_base+0x2400)
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#define SSUSB_USB2_CSR_BASE (u3_base+0x3400)
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/*
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* 0x1128_0000 for sifslv register in Infra
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*/
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#define SSUSB_SIFSLV_IPPC_BASE (u3_ippc_base)
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#include "ssusb_dev_c_header.h"
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#include "ssusb_epctl_csr_c_header.h"
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/* usb3_mac / usb3_sys do not exist in U2 ONLY IP */
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#include "ssusb_usb3_mac_csr_c_header.h"
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#include "ssusb_usb3_sys_csr_c_header.h"
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#include "ssusb_usb2_csr_c_header.h"
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#include "ssusb_sifslv_ippc_c_header.h"
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#include "mtk-phy.h"
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#ifdef EXT_VBUS_DET
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#define FPGA_REG 0xf0008098
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#define VBUS_RISE_BIT (1<<11) /* W1C */
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#define VBUS_FALL_BIT (1<<12) /* W1C */
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#define VBUS_MSK (VBUS_RISE_BIT | VBUS_FALL_BIT)
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#define VBUS_RISE_IRQ 13
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#define VBUS_FALL_IRQ 14
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#endif
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#define USB_IRQ 146
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#define RISC_SIZE_1B 0x0
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#define RISC_SIZE_2B 0x1
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#define RISC_SIZE_4B 0x2
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#define USB_FIFO(ep_num) (U3D_FIFO0+ep_num*0x10)
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#define USB_FIFOSZ_SIZE_8 (0x03)
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#define USB_FIFOSZ_SIZE_16 (0x04)
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#define USB_FIFOSZ_SIZE_32 (0x05)
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#define USB_FIFOSZ_SIZE_64 (0x06)
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#define USB_FIFOSZ_SIZE_128 (0x07)
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#define USB_FIFOSZ_SIZE_256 (0x08)
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#define USB_FIFOSZ_SIZE_512 (0x09)
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#define USB_FIFOSZ_SIZE_1024 (0x0A)
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#define USB_FIFOSZ_SIZE_2048 (0x0B)
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#define USB_FIFOSZ_SIZE_4096 (0x0C)
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#define USB_FIFOSZ_SIZE_8192 (0x0D)
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#define USB_FIFOSZ_SIZE_16384 (0x0E)
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#define USB_FIFOSZ_SIZE_32768 (0x0F)
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/* U3D_EP0CSR */
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#define CSR0_SETUPEND (0x00200000) /* /removed, use SETUPENDISR */
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#define CSR0_FLUSHFIFO (0x01000000) /* /removed */
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#define CSR0_SERVICESETUPEND (0x08000000) /* /removed, W1C SETUPENDISR */
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#define EP0_W1C_BITS (~(EP0_RXPKTRDY | EP0_SETUPPKTRDY | EP0_SENTSTALL))
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/* U3D_TX1CSR0 */
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#define USB_TXCSR_FLUSHFIFO (0x00100000) /* removed */
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#define TX_W1C_BITS (~(TX_SENTSTALL))
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/* USB_RXCSR */
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#define USB_RXCSR_FLUSHFIFO (0x00100000) /* removed */
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#define RX_W1C_BITS (~(RX_SENTSTALL|RX_RXPKTRDY))
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#define BIT0 (1<<0)
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#define BIT16 (1<<16)
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#define TYPE_BULK (0x00)
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#define TYPE_INT (0x10)
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#define TYPE_ISO (0x20)
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#define TYPE_MASK (0x30)
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/* QMU macros */
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#define USB_QMU_RQCSR(n) (U3D_RXQCSR1+0x0010*((n)-1))
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#define USB_QMU_RQSAR(n) (U3D_RXQSAR1+0x0010*((n)-1))
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#define USB_QMU_RQCPR(n) (U3D_RXQCPR1+0x0010*((n)-1))
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#define USB_QMU_RQLDPR(n) (U3D_RXQLDPR1+0x0010*((n)-1))
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#define USB_QMU_TQCSR(n) (U3D_TXQCSR1+0x0010*((n)-1))
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#define USB_QMU_TQSAR(n) (U3D_TXQSAR1+0x0010*((n)-1))
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#define USB_QMU_TQCPR(n) (U3D_TXQCPR1+0x0010*((n)-1))
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#define QMU_Q_START (0x00000001)
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#define QMU_Q_RESUME (0x00000002)
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#define QMU_Q_STOP (0x00000004)
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#define QMU_Q_ACTIVE (0x00008000)
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#define QMU_TX_EN(n) (BIT0<<(n))
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#define QMU_RX_EN(n) (BIT16<<(n))
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#define QMU_TX_CS_EN(n) (BIT0<<(n))
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#define QMU_RX_CS_EN(n) (BIT16<<(n))
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#define QMU_TX_ZLP(n) (BIT0<<(n))
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#define QMU_RX_MULTIPLE(n) (BIT16<<((n)-1))
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#define QMU_RX_ZLP(n) (BIT0<<(n))
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#define QMU_RX_COZ(n) (BIT16<<(n))
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#define QMU_RX_EMPTY(n) (BIT16<<(n))
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#define QMU_TX_EMPTY(n) (BIT0<<(n))
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#define QMU_RX_DONE(n) (BIT16<<(n))
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#define QMU_TX_DONE(n) (BIT0<<(n))
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#define QMU_RX_ZLP_ERR(n) (BIT16<<(n))
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#define QMU_RX_EP_ERR(n) (BIT0<<(n))
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#define QMU_RX_LEN_ERR(n) (BIT16<<(n))
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#define QMU_RX_CS_ERR(n) (BIT0<<(n))
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#define QMU_TX_LEN_ERR(n) (BIT16<<(n))
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#define QMU_TX_CS_ERR(n) (BIT0<<(n))
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/**
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* @MAC value Definition
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*/
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/* U3D_LINK_STATE_MACHINE */
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#define STATE_RESET (0)
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#define STATE_DISABLE (1)
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#define STATE_DISABLE_EXIT (2)
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#define STATE_SS_INACTIVE_QUITE (3)
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#define STATE_SS_INACTIVE_DISC_DETECT (4)
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#define STATE_RX_DETECT_RESET (5)
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#define STATE_RX_DETECT_ACTIVE (6)
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#define STATE_RX_DETECT_QUITE (7)
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#define STATE_POLLING_LFPS (8)
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#define STATE_POLLING_RXEQ (9)
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#define STATE_POLLING_ACTIVE (10)
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#define STATE_POLLING_CONFIGURATION (11)
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#define STATE_POLLING_IDLE (12)
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#define STATE_U0_STATE (13)
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#define STATE_U1_STATE (14)
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#define STATE_U1_TX_PING (15)
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#define STATE_U1_EXIT (16)
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#define STATE_U2_STATE (17)
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#define STATE_U2_DETECT (18)
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#define STATE_U2_EXIT (19)
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#define STATE_U3_STATE (20)
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#define STATE_U3_DETECT (21)
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#define STATE_U3_EXIT (22)
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#define STATE_COMPLIANCE (23)
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#define STATE_RECOVERY_ACTIVE (24)
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#define STATE_RECOVERY_CONFIGURATION (25)
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#define STATE_RECOVERY_IDLE (26)
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#define STATE_LOOPBACK_ACTIVE_MASTER (27)
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#define STATE_LOOPBACK_ACTIVE_SLAVE (28)
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/* TODO: remove these definitions */
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#if 1
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/* DEVICE_CONTROL */
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#define USB_DEVCTL_SESSION (0x1)
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#define USB_DEVCTL_HOSTREQUEST (0x2)
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#define USB_DEVCTL_HOSTMODE (0x4)
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#define USB_DEVCTL_LS_DEV (0x5)
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#define USB_DEVCTL_FS_DEV (0x6)
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#define USB_DEVCTL_BDEVICE (0x80)
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#define USB_DEVCTL_VBUSMASK (0x18)
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#define USB_DEVCTL_VBUSVALID (0x18)
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#define USB_DEVCTL_VBUS_OFFSET (0x3)
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#endif
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#endif /* USB_HW_H */
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