Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
89 lines
2.1 KiB
C
89 lines
2.1 KiB
C
/*
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* Copyright (C) 2015 MediaTek Inc.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cmdq_core.h>
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#include <cmdq_reg.h>
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#if defined(CONFIG_MTK_LEGACY)
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#include <mach/mt_clkmgr.h>
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#endif
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#include "jpeg_drv_reg.h"
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#include "jpeg_cmdq.h"
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int32_t cmdqJpegClockOn(uint64_t engineFlag)
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{
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#if 0
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if (engineFlag & (1 << CMDQ_ENG_JPEG_DEC))
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enable_clock(MT65XX_PDN_MM_JPEG_DEC, "JPEG");
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if (engineFlag & (1 << CMDQ_ENG_JPEG_ENC_PASS1))
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enable_clock(MT65XX_PDN_MM_JPEG_DEC, "JPEG");
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if (engineFlag & (1 << CMDQ_ENG_JPEG_ENC_PASS2))
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enable_clock(MT65XX_PDN_MM_JPEG_DEC, "JPEG");
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#endif
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return 0;
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}
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int32_t cmdqJpegDumpInfo(uint64_t engineFlag, int level)
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{
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return 0;
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}
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int32_t cmdqJpegResetEng(uint64_t engineFlag)
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{
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if (engineFlag & (1 << CMDQ_ENG_JPEG_DEC)) {
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IMG_REG_WRITE(0x0000FFFF, REG_ADDR_JPGDEC_INTERRUPT_STATUS);
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IMG_REG_WRITE(0x00, REG_ADDR_JPGDEC_RESET);
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IMG_REG_WRITE(0x01, REG_ADDR_JPGDEC_RESET);
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IMG_REG_WRITE(0x00, REG_ADDR_JPGDEC_RESET);
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IMG_REG_WRITE(0x10, REG_ADDR_JPGDEC_RESET);
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}
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if (engineFlag & (1 << CMDQ_ENG_JPEG_ENC)) {
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IMG_REG_WRITE(0, REG_ADDR_JPEG_ENC_RSTB);
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IMG_REG_WRITE(1, REG_ADDR_JPEG_ENC_RSTB);
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}
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if (engineFlag & (1 << CMDQ_ENG_JPEG_REMDC)) {
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IMG_REG_WRITE(0, REG_ADDR_JPEG_ENC_PASS2_RSTB);
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IMG_REG_WRITE(1, REG_ADDR_JPEG_ENC_PASS2_RSTB);
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}
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return 0;
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}
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int32_t cmdqJpegClockOff(uint64_t engineFlag)
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{
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#if 0
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if (engineFlag & (1 << CMDQ_ENG_JPEG_DEC))
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disable_clock(MT65XX_PDN_MM_JPEG_DEC, "JPEG");
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if (engineFlag & (1 << CMDQ_ENG_JPEG_ENC_PASS1))
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disable_clock(MT65XX_PDN_MM_JPEG_DEC, "JPEG");
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if (engineFlag & (1 << CMDQ_ENG_JPEG_ENC_PASS2))
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disable_clock(MT65XX_PDN_MM_JPEG_DEC, "JPEG");
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#endif
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return 0;
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}
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