threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
62 lines
2.1 KiB
C
62 lines
2.1 KiB
C
/*
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* Copyright (C) 2019 MediaTek Inc.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __MT_PMIC_WRAP_H__
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#define __MT_PMIC_WRAP_H__
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#include <linux/types.h>
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#include <linux/device.h>
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#define PWRAP_READ 0
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#define PWRAP_WRITE 1
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struct mt_pmic_wrap_driver {
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struct device_driver driver;
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s32 (*wacs2_hal)(u32 write, u32 adr, u32 wdata, u32 *rdata);
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s32 (*show_hal)(char *buf);
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s32 (*store_hal)(const char *buf, size_t count);
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s32 (*suspend)(void);
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void (*resume)(void);
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};
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/* ------external API for pmic_wrap user-------------------------------*/
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s32 pwrap_read(u32 adr, u32 *rdata);
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s32 pwrap_write(u32 adr, u32 wdata);
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s32 pwrap_wacs2(u32 write, u32 adr, u32 wdata, u32 *rdata);
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/*_____________ROME only_____________________________________________*/
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/********************************************************************/
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/* return value : EINT_STA: [0]: CPU IRQ status in MT6331 */
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/* [1]: MD32 IRQ status in MT6331 */
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/* [2]: CPU IRQ status in MT6332 */
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/* [3]: RESERVED */
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/********************************************************************/
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u32 pmic_wrap_eint_status(void);
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/********************************************************************/
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/* set value(W1C) : EINT_CLR: [0]: CPU IRQ status in MT6331 */
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/* [1]: MD32 IRQ status in MT6331 */
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/* [2]: CPU IRQ status in MT6332 */
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/* [3]: RESERVED */
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/* para: offset is shift of clear bit which needs to clear */
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/********************************************************************/
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void pmic_wrap_eint_clr(int offset);
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/*--------------------------------------------------------------------*/
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u32 mt_pmic_wrap_eint_status(void);
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void mt_pmic_wrap_eint_clr(int offset);
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s32 pwrap_init(void);
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struct mt_pmic_wrap_driver *get_mt_pmic_wrap_drv(void);
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#endif /* __MT_PMIC_WRAP_H__ */
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