threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
262 lines
8.4 KiB
C
262 lines
8.4 KiB
C
/*
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* Copyright (C) 2015 MediaTek Inc.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __MD_SYS1_PLATFORM_H__
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#define __MD_SYS1_PLATFORM_H__
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#include <linux/skbuff.h>
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#include "ccif_hif_platform.h"
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#include <mt-plat/mtk_secure_api.h>
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#include "ccci_platform.h"
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/* this is the platform header file for CLDMA MODEM, not just CLDMA! */
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#define AP_REMAP_ADDR_FOR_MD_CLDMA 0xA0000000
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/* Modem WDT */
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/* BASE_ADDR_MDRSTCTL+ */
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#define REG_MDRSTCTL_WDTCR (0x0000) /*WDT_MODE*/
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#define REG_MDRSTCTL_WDTRR (0x0010) /*WDT_RESTART*/
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#define REG_MDRSTCTL_WDTIR (0x023C) /*LENGTH*/
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#define REG_MDRSTCTL_WDTSR (0x0034) /*WDT_STATUS*/
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#define WDT_MD_MODE REG_MDRSTCTL_WDTCR
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#define WDT_MD_LENGTH REG_MDRSTCTL_WDTIR
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#define WDT_MD_RESTART REG_MDRSTCTL_WDTRR
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#define WDT_MD_STA REG_MDRSTCTL_WDTSR
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#define WDT_MD_MODE_KEY (0x55000030)
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/* L1_BASE_ADDR_L1RGU+ */
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#define REG_L1RSTCTL_WDT_MODE (0x0000)
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#define REG_L1RSTCTL_WDT_LENGTH (0x0004)
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#define REG_L1RSTCTL_WDT_RESTART (0x0008)
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#define REG_L1RSTCTL_WDT_STA (0x000C)
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#define REG_L1RSTCTL_WDT_SWRST (0x001C)
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#define L1_WDT_MD_MODE_KEY (0x00002200)
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/* MD1 PLL */
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/* MD_CLKSW_BASE+ */
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#define R_CLKSEL_CTL (0x0024)
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/*Bit 17: RF1_CKSEL, Bit 16: INTF_CKSEL, Bit 15: MD2G_CKSEL, Bit 14: DFE_CKSEL
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*Bit 13: CMP_CKSEL, Bit 12: ICC_CKSEL, Bit 11: IMC_CKSEL, Bit 10: EQ_CKSEL
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*Bit 9: BRP_CKSEL, Bit 8: L1MCU_CKSEL, Bit 6-5: ATB_SRC_CKSEL,
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*Bit 4: ATB_CKSEL, Bit 3: DBG_CKSEL, Bit 2: ARM7_CKSEL
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*Bit 1: PSMCU_CKSEL, Bit 0: BUS_CKSEL
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*/
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#define R_FLEXCKGEN_SEL0 (0x0028)
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/* Bit 29-28: EQ_CLK src = EQPLL
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* Bit 26-24: EQ+DIVSEL, divided-by bit[2:0]+1
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* Bit 21-20: BRP_CLK src = IMCPLL
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* Bit 13-12: ARM7_CLK src = DFEPLL
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* Bit 5-4: BUS_CLK src = EQPLL
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* Bit 2-0: BUS_DIVSEL, divided-by bit[2:0]+1
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*/
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#define R_FLEXCKGEN_SEL1 (0x002C)
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#define R_FLEXCKGEN_SEL2 (0x0044)
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/* Bit 0: PSMCUPLL_RDY, Bit 1: L1MCUPLL_RDY */
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#define R_PLL_STS (0x0040)
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#define R_FLEXCKGEN_STS0 (0x0030)
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/* Bit 31: EQ_CK_RDY */
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/* Bit 23: BRP_CK_RDY */
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/* Bit 7: BUS_CK_RDY */
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#define R_FLEXCKGEN_STS1 (0x0034)
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/* Bit 31: DFE_CK_RDY
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* Bit 23: CMP_CK_RDY
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* Bit 15: ICC_CK_RDY
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* Bit 7: IMC_CK_RDY
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*/
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#define R_FLEXCKGEN_STS2 (0x0048)
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/* Bit 15: INTF_CK_RDY, Bit 23: MD2G_CK_RDY */
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/* PSMCU DCM: MD_GLOBAL_CON_DCM_BASE+ */
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/* Bit 26-20: DBC_CNT, Bit 16-12: IDLE_FSEL, Bit 2: DBC_EN, Bit 1: DCM_EN */
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#define R_PSMCU_DCM_CTL0 (0x0010)
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/* Bit 5: APB_LOAD_TOG, Bit 4-0: APB_SEL */
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#define R_PSMCU_DCM_CTL1 (0x0014)
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/* MD_GLOBAL_CON_DCM_BASE+ */
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/* Bit 26-20: DBC_CNT, Bit 16-12: IDLE_FSEL, Bit 2: DBC_EN, Bit 1: DCM_EN */
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#define R_ARM7_DCM_CTL0 (0x0020)
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/* Bit 5: APB_LOAD_TOG, Bit 4-0: APB_SEL */
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#define R_ARM7_DCM_CTL1 (0x0024)
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#define MD_GLOBAL_CON_DUMMY (0x1000)
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#define MD_PLL_MAGIC_NUM (0x67550000)
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/* MDSYS_CLKCTL_BASE+ */
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#define R_DCM_SHR_SET_CTL (0x0004)
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/* Bit 16: BUS_PLL_SWITCH
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* Bit 15: BUS_QUARTER_FREQ_SEL
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* Bit 14: BUS_SLOW_FREQ
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* Bit 12-8: HFBUS_SFSEL
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* Bit 4-0: HFBUS_FSEL
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*/
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#define R_LTEL2_BUS_DCM_CTL (0x0010)
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#define R_MDDMA_BUS_DCM_CTL (0x0014)
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#define R_MDREG_BUS_DCM_CTL (0x0018)
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#define R_MODULE_BUS2X_DCM_CTL (0x001C)
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#define R_MODULE_BUS1X_DCM_CTL (0x0020)
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#define R_MDINFRA_CKEN (0x0044)
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/* Bit 31: PSPERI_MAS_DCM_EN
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* Bit 30: PSPERI_SLV_DCM_EN
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* Bit 4: SOE_CKEN
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* Bit 3: BUSREC_CKEN
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* Bit 2: BUSMON_CKEN
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* Bit 1: MDUART2_CKEN
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* Bit 0: MDUART1_CKEN
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*/
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#define R_MDPERI_CKEN (0x0048)
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/* Bit 31: MDDBGSYS_DCM_EN
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* Bit 21: USB0_LINK_CK_SEL
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* Bit 20: USB1_LINK_CK_SEL
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* Bit 17: TRACE_CKEN
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* Bit 16: MDPERI_MISCREG_CKEN
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* Bit 15: PCCIF_CKEN
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* Bit 14: MDEINT_CKEN
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* Bit 13: MDCFGCTL_CKEN
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* Bit 12: MDRGU_CKEN
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* Bit 11: A7OST_CKEN
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* Bit 10: MDOST_CKEN
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* Bit 9: MDTOPSM_CKEN
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* Bit 8: MDCIRQ_CKEN
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* Bit 7: MDECT_CKEN
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* Bit 6: USIM2_CKEN
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* Bit 5: USIM1_CKEN
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* Bit 4: GPTMLITE_CKEN
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* Bit 3: MDGPTM_CKEN
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* Bit 2: I2C_CKEN
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* Bit 1: MDGDMA_CKEN
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* Bit 0: MDUART0_CKEN
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*/
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#define R_MDPERI_DCM_MASK (0x0064)
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/* Bit 12: MDRGU_DCM_MASK
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* Bit 11: A7OST_DCM_MASK
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* Bit 10: MDOST_DCM_MASK
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* Bit 9: MDTOPSM_DCM_MASK
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*/
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#define R_PSMCU_AO_CLK_CTL (0x00C0)
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/* MD_PERI_MISC_BASE+ */
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#define R_L1_PMS (0x00C4)
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/* PMDL1A0_BASE+ */
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/* Bit 7: 0: clock do not from PLL, 1: clock from PLL */
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#define REG_DCM_PLLCK_SEL (0x0188)
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#define R_L1MCU_PWR_AWARE (0x0190)
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#define R_L1AO_PWR_AWARE (0x0194)
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#define R_BUSL2DCM_CON3 (0x0198)
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#define R_L1MCU_DCM_CON2 (0x0184)
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#define R_L1MCU_DCM_CON (0x0180)
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/* ap_mixed_base+ */
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/* ((UINT32P)(APMIXED_BASE+0x0)) */
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#define AP_PLL_CON0 0x0
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/* ((UINT32P)(APMIXED_BASE+0x02C8)) */
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#define MDPLL1_CON0 0x3A0
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struct ccci_clk_node {
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struct clk *clk_ref;
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unsigned char *clk_name;
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};
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struct md_pll_reg {
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void __iomem *md_top_clkSW;
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void __iomem *md_top_Pll;
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void __iomem *md_boot_stats0;
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void __iomem *md_boot_stats1;
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};
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struct md_hw_info {
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/* HW info - Register Address */
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unsigned long md_rgu_base;
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unsigned long ap_mixed_base;
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void __iomem *ap_topclkgen_base;
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unsigned long md_boot_slave_Vector;
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unsigned long md_boot_slave_Key;
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unsigned long md_boot_slave_En;
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unsigned long ap_ccif_base;
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unsigned long md_ccif_base;
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unsigned int sram_size;
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/* HW info - Interrutpt ID */
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unsigned int ap_ccif_irq0_id;
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unsigned int ap_ccif_irq1_id;
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unsigned int md_wdt_irq_id;
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unsigned int ap2md_bus_timeout_irq_id;
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void __iomem *md_pcore_pccif_base;
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/* HW info - Interrupt flags */
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unsigned long ap_ccif_irq0_flags;
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unsigned long ap_ccif_irq1_flags;
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unsigned long md_wdt_irq_flags;
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unsigned long ap2md_bus_timeout_irq_flags;
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void *hif_hw_info;
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};
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struct cldma_hw_info {
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unsigned long cldma_ap_ao_base;
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unsigned long cldma_ap_pdn_base;
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unsigned int cldma_irq_id;
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unsigned long cldma_irq_flags;
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};
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enum MD_REG_ID {
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MD_REG_AP_MDSRC_REQ = 0,
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MD_REG_PC_MONITOR,
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MD_REG_PLL_REG,
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MD_REG_BUS,
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MD_REG_MDMCU_BUSMON,
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MD_REG_MDINFRA_BUSMON,
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MD_REG_ECT,
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MD_REG_TOPSM_REG,
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MD_REG_MD_RGU_REG,
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MD_REG_OST_STATUS,
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MD_REG_CSC_REG,
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MD_REG_ELM_REG,
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};
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#define mdreg_write32(reg_id, value) \
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mt_secure_call(MTK_SIP_KERNEL_CCCI_GET_INFO, reg_id, value, 0, 0)
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int ccci_modem_remove(struct platform_device *dev);
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void ccci_modem_shutdown(struct platform_device *dev);
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int ccci_modem_suspend(struct platform_device *dev, pm_message_t state);
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int ccci_modem_resume(struct platform_device *dev);
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int ccci_modem_pm_suspend(struct device *device);
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int ccci_modem_pm_resume(struct device *device);
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int ccci_modem_pm_restore_noirq(struct device *device);
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int md_cd_power_on(struct ccci_modem *md);
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int md_cd_power_off(struct ccci_modem *md, unsigned int timeout);
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int md_cd_soft_power_off(struct ccci_modem *md, unsigned int mode);
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int md_cd_soft_power_on(struct ccci_modem *md, unsigned int mode);
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int md_cd_let_md_go(struct ccci_modem *md);
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void md_cd_lock_cldma_clock_src(int locked);
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void md_cd_lock_modem_clock_src(int locked);
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int md_cd_bootup_cleanup(struct ccci_modem *md, int success);
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int md_cd_low_power_notify(struct ccci_modem *md,
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enum LOW_POEWR_NOTIFY_TYPE type, int level);
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int md_cd_get_modem_hw_info(struct platform_device *dev_ptr,
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struct ccci_dev_cfg *dev_cfg, struct md_hw_info *hw_info);
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int md_cd_io_remap_md_side_register(struct ccci_modem *md);
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void md_cd_dump_debug_register(struct ccci_modem *md);
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void md_cd_dump_md_bootup_status(struct ccci_modem *md);
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void md_cd_get_md_bootup_status(struct ccci_modem *md,
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unsigned int *buff, int length);
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void md_cd_check_emi_state(struct ccci_modem *md, int polling);
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void cldma_dump_register(struct md_cd_ctrl *md_ctrl);
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void md_cldma_hw_reset(unsigned char md_id);
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int md_cd_pccif_send(struct ccci_modem *md, int channel_id);
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void md_cd_dump_pccif_reg(struct ccci_modem *md);
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int md_cd_vcore_config(unsigned int md_id, unsigned int hold_req);
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/* ADD_SYS_CORE */
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int ccci_modem_syssuspend(void);
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void ccci_modem_sysresume(void);
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void md_cd_check_md_DCM(struct md_cd_ctrl *md_ctrl);
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extern unsigned long infra_ao_base;
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extern unsigned int devapc_check_flag;
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extern void ccci_mem_dump(int md_id, void *start_addr, int len);
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#endif /* __CLDMA_PLATFORM_H__ */
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