threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
96 lines
2.9 KiB
C
96 lines
2.9 KiB
C
/*
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* Copyright (C) 2015 MediaTek Inc.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __CCIF_HIF_PLATFORM_H__
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#define __CCIF_HIF_PLATFORM_H__
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#include "ccci_config.h"
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#include <mt-plat/sync_write.h>
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extern unsigned int devapc_check_flag;
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#define ccif_write32(b, a, v) \
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do { \
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if (devapc_check_flag == 1) \
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mt_reg_sync_writel(v, (b) + (a)); \
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} while (0)
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#define ccif_write16(b, a, v) mt_reg_sync_writew(v, (b)+(a))
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#define ccif_write8(b, a, v) mt_reg_sync_writeb(v, (b)+(a))
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#define ccif_read32(b, a) \
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((devapc_check_flag == 1) ? ioread32((void __iomem *)((b)+(a))) : 0)
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#define ccif_read16(b, a) ioread16((void __iomem *)((b)+(a)))
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#define ccif_read8(b, a) ioread8((void __iomem *)((b)+(a)))
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/*CCIF */
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#define APCCIF_CON (0x00)
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#define APCCIF_BUSY (0x04)
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#define APCCIF_START (0x08)
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#define APCCIF_TCHNUM (0x0C)
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#define APCCIF_RCHNUM (0x10)
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#define APCCIF_ACK (0x14)
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#define APCCIF_CHDATA (0x100)
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#if (MD_GENERATION <= 6292)
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#define RINGQ_BASE (8)
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#define RINGQ_SRAM (7)
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#define RINGQ_EXP_BASE (0)
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#define CCIF_CH_NUM 16
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#define AP_MD_CCB_WAKEUP (8)
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#else
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#define RINGQ_BASE (0)
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#define RINGQ_SRAM (15)
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#define RINGQ_EXP_BASE (15)
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#define CCIF_CH_NUM 24
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#define AP_MD_CCB_WAKEUP (7)
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#endif
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/*AP to MD*/
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#define H2D_EXCEPTION_ACK (RINGQ_EXP_BASE+1)
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#define H2D_EXCEPTION_CLEARQ_ACK (RINGQ_EXP_BASE+2)
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#define H2D_FORCE_MD_ASSERT (RINGQ_EXP_BASE+3)
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#define H2D_MPU_FORCE_ASSERT (RINGQ_EXP_BASE+4)
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#define H2D_SRAM (RINGQ_SRAM)
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#define H2D_RINGQ0 (RINGQ_BASE+0)
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#define H2D_RINGQ1 (RINGQ_BASE+1)
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#define H2D_RINGQ2 (RINGQ_BASE+2)
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#define H2D_RINGQ3 (RINGQ_BASE+3)
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#define H2D_RINGQ4 (RINGQ_BASE+4)
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#define H2D_RINGQ5 (RINGQ_BASE+5)
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#define H2D_RINGQ6 (RINGQ_BASE+6)
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#define H2D_RINGQ7 (RINGQ_BASE+7)
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/*MD to AP*/
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#define CCIF_HW_CH_RX_RESERVED \
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((1 << (RINGQ_EXP_BASE+0)) | (1 << (RINGQ_EXP_BASE+5)))
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#define D2H_EXCEPTION_INIT (RINGQ_EXP_BASE+1)
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#define D2H_EXCEPTION_INIT_DONE (RINGQ_EXP_BASE+2)
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#define D2H_EXCEPTION_CLEARQ_DONE (RINGQ_EXP_BASE+3)
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#define D2H_EXCEPTION_ALLQ_RESET (RINGQ_EXP_BASE+4)
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#define AP_MD_SEQ_ERROR (RINGQ_EXP_BASE+6)
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#define D2H_SRAM (RINGQ_SRAM)
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#define D2H_RINGQ0 (RINGQ_BASE+0)
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#define D2H_RINGQ1 (RINGQ_BASE+1)
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#define D2H_RINGQ2 (RINGQ_BASE+2)
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#define D2H_RINGQ3 (RINGQ_BASE+3)
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#define D2H_RINGQ4 (RINGQ_BASE+4)
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#define D2H_RINGQ5 (RINGQ_BASE+5)
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#define D2H_RINGQ6 (RINGQ_BASE+6)
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#define D2H_RINGQ7 (RINGQ_BASE+7)
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/* peer */
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#define AP_MD_PEER_WAKEUP (RINGQ_EXP_BASE+5)
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#endif /*__CCIF_HIF_PLATFORM_H__*/
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