threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
150 lines
4.4 KiB
C
150 lines
4.4 KiB
C
/*
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* Copyright (C) 2015 MediaTek Inc.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __MODEM_REG_BASE_H__
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#define __MODEM_REG_BASE_H__
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/* ============================================================ */
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/* Modem 1 part */
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/* ============================================================ */
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/* MD peripheral register: MD bank8; AP bank2 */
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#define CLDMA_AP_BASE 0x200F0000
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#define CLDMA_AP_LENGTH 0x3000
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#define CLDMA_MD_BASE 0x200E0000
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#define CLDMA_MD_LENGTH 0x3000
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#define MD_BOOT_VECTOR_EN 0x20000024
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#define MD_PCORE_PCCIF_BASE 0x20510000
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#define MD_GLOBAL_CON0 0x20000450
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#define MD_GLOBAL_CON0_CLDMA_BIT 12
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#define CCIF_SRAM_SIZE 512
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#define BASE_ADDR_MDRSTCTL 0x200f0000 /* From md, no use by AP directly */
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#define L1_BASE_ADDR_L1RGU 0x26010000 /* From md, no use by AP directly */
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#define MD_RGU_BASE (BASE_ADDR_MDRSTCTL + 0x100) /* AP use */
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#define L1_RGU_BASE L1_BASE_ADDR_L1RGU /* AP use */
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/* MD1 PLL */
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#define MDTOP_PLLMIXED_BASE (0x20140000)
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#define MDTOP_PLLMIXED_LENGTH (0x1000)
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#define MDTOP_CLKSW_BASE (0x20150000)
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#define MDTOP_CLKSW_LENGTH (0x1000)
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#define MD_PERI_MISC_BASE (0x20060000)
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#define MD_PERI_MISC_LEN 0xD0
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#define MDL1A0_BASE (0x260F0000)
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#define MDL1A0_LEN 0x200
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#define MDSYS_CLKCTL_BASE (0x20120000)
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#define MDSYS_CLKCTL_LEN 0xD0
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/*#define L1_BASE_MADDR_MDL1_CONF (0x260F0000)*/
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/* MD Exception dump register list start[ */
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#define MD1_OPEN_DEBUG_APB_CLK (0x10006000)
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/* PC Monitor */
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#define MD_PC_MONITOR_BASE (0x0D0D9000)
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#define MD_PC_MONITOR_LEN (0x1000)
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/* PLL reg (clock control) */
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/** MD CLKSW **/
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#define MD_CLKSW_BASE (0x0D0D6000)
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#define MD_CLKSW_LEN 0xF08
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/** MD PLLMIXED **/
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#define MD_PLL_MIXED_BASE (0x0D0D4000)
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#define MD_PLL_MIXED_LEN (0xF14)
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/** MD CLKCTL **/
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#define MD_CLKCTL_BASE (0x0D0C3800)
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#define MD_CLKCTL_LEN 0x130
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/** MD GLOBALCON **/
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#define MD_GLOBALCON_BASE (0x0D0D5000)
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#define MD_GLOBALCON_LEN 0x1000
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/* BUS reg */
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#define MD_BUS_REG_BASE0 (0x0D0C2000)/* mdmcu_misc_reg */
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#define MD_BUS_REG_LEN0 0x100
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#define MD_BUS_REG_BASE1 (0x0D0C7000)/* mdinfra_misc_reg */
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#define MD_BUS_REG_LEN1 0xAC
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#define MD_BUS_REG_BASE2 (0x0D0C9000)/* cm2_misc */
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#define MD_BUS_REG_LEN2 0xAC
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#define MD_BUS_REG_BASE3 (0x0D0E0000)/* modeml1_ao_config */
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#define MD_BUS_REG_LEN3 0x6C
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/* BUSREC */
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#define MD_MCU_MO_BUSREC_BASE (0x0D0C6000)
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#define MD_MCU_MO_BUSREC_LEN 0x1000
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#define MD_INFRA_BUSREC_BASE (0x0D0C8000)
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#define MD_INFRA_BUSREC_LEN 0x1000
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#define MD_BUSREC_LAY_BASE (0x0D0C2500)
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#define MD_BUSREC_LAY_LEN 0x8
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/* ECT */
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/* MD ECT triggerIn/Out status */
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#define MD_ECT_REG_BASE0 (0x0D0CC130)
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#define MD_ECT_REG_LEN0 0x8
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/* ModemSys ECT triggerIn/Out status */
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#define MD_ECT_REG_BASE1 (0x0D0CD130)
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#define MD_ECT_REG_LEN1 0x8
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/* MD32 ECT status */
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#define MD_ECT_REG_BASE2 (0x0D0CE000)
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#define MD_ECT_REG_LEN2 0x20
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/* TOPSM reg */
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#define MD_TOPSM_REG_BASE (0x0200D0000)
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#define MD_TOPSM_REG_LEN 0x8E4
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/* MD RGU reg */
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#define MD_RGU_REG_BASE (0x0200F0100)
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#define MD_RGU_REG_LEN 0x400
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/* OST status */
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#define MD_OST_STATUS_BASE 0x200E0000
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#define MD_OST_STATUS_LEN 0x300
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/* CSC reg */
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#define MD_CSC_REG_BASE 0x20100000
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#define MD_CSC_REG_LEN 0x214
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/* ELM reg */
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#define MD_ELM_REG_BASE 0x20350000
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#define MD_ELM_REG_LEN 0x480
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/*MD bootup register*/
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#define MD1_CFG_BASE (0x1020E300)
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#define MD1_CFG_BOOT_STATS0 (MD1_CFG_BASE+0x00)
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#define MD1_CFG_BOOT_STATS1 (MD1_CFG_BASE+0x04)
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/* MD Exception dump register list end] */
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#define MD_SRAM_PD_PSMCUSYS_SRAM_BASE (0x200D0000)
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#define MD_SRAM_PD_PSMCUSYS_SRAM_LEN (0xB00)
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/*
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* ============================================================
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* Modem 3 part
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* ============================================================
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* need modify, haow
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*/
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#define MD3_BOOT_VECTOR 0x30190000
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#define MD3_BOOT_VECTOR_KEY 0x3019379C
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#define MD3_BOOT_VECTOR_EN 0x30195488
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#define MD3_BOOT_VECTOR_VALUE 0x00000000
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#define MD3_BOOT_VECTOR_KEY_VALUE 0x3567C766
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#define MD3_BOOT_VECTOR_EN_VALUE 0xA3B66175
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#define MD3_RGU_BASE 0x3A001080
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#define APCCIF1_SRAM_SIZE 512
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#endif /* __MODEM_REG_BASE_H__ */
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