threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
146 lines
3.5 KiB
C
146 lines
3.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2019 MediaTek Inc.
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*/
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#ifndef __DEVAPC_MT6785_H__
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#define __DEVAPC_MT6785_H__
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/******************************************************************************
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* VARIABLE DEFINATION
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******************************************************************************/
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/* dbg status default setting */
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#define PLAT_DBG_UT_DEFAULT false
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#define PLAT_DBG_KE_DEFAULT true
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#define PLAT_DBG_AEE_DEFAULT true
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#define PLAT_DBG_DAPC_DEFAULT false
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#define PLAT_VIO_CFG_MAX_IDX 445
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#define PLAT_VIO_MAX_IDX 525
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#define PLAT_VIO_MASK_STA_NUM 17
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#define PLAT_VIO_SHIFT_MAX_BIT 25
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/******************************************************************************
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* DATA STRUCTURE & FUNCTION DEFINATION
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******************************************************************************/
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const char *bus_id_to_master(int bus_id, uint32_t vio_addr, int vio_idx);
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const char *index_to_subsys(unsigned int index);
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/* violation index corresponds to subsys */
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enum SMI_INDEX {
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SMI_LARB0 = 268,
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SMI_LARB1 = 269,
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SMI_COMMON = 270,
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SMI_LARB5 = 281,
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SMI_LARB2 = 295,
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VENCSYS_SMI_LARB = 298,
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VDECSYS_SMI_LARB = 307,
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SMI_LARB6 = 314,
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SMI_LARB3 = 315,
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};
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enum MFGSYS_INDEX {
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MFGSYS_START = 232,
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MFGSYS_END = 244,
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};
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enum MMSYS_INDEX {
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MMSYS_MDP_START = 245,
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MMSYS_MDP_END = 252,
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MMSYS_DISP_START = 253,
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MMSYS_DISP_END = 271,
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MMSYS_MDP2_START = 272,
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MMSYS_MDP2_END = 279,
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};
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enum IMGSYS_INDEX {
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IMGSYS_START = 280,
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IMGSYS_END = 296,
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};
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enum VENCSYS_INDEX {
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VENCSYS_START = 297,
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VENCSYS_END = 305,
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};
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enum VDECSYS_INDEX {
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VDECSYS_START = 306,
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VDECSYS_END = 312,
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};
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enum CAMSYS_INDEX {
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CAMSYS_START = 313,
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CAMSYS_END = 376,
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CAMSYS_SENINF_START = 377,
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CAMSYS_SENINF_END = 392,
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CAMSYS_P1_START = 393,
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CAMSYS_P1_END = 414,
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CAMSYS_CCU_START = 415,
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CAMSYS_CCU_END = 423,
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};
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enum APUSYS_INDEX {
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APUSYS_START = 424,
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APUSYS_END = 445,
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};
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enum OTHER_TYPES_INDEX {
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SRAMROM_VIO_INDEX = 511,
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TOPAXI_SI0_DECERR = 503,
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PERIAXI_SI1_DECERR = 505,
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};
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enum BUSID_LENGTH {
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PERIAXI_INT_MI_BIT_LENGTH = 5,
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TOPAXI_MI0_BIT_LENGTH = 12,
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};
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/* bit == 2 means don't care */
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struct PERIAXI_ID_INFO {
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const char *master;
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uint8_t bit[PERIAXI_INT_MI_BIT_LENGTH];
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};
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struct TOPAXI_ID_INFO {
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const char *master;
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uint8_t bit[TOPAXI_MI0_BIT_LENGTH];
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};
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/******************************************************************************
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* PLATFORM DEFINATION
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******************************************************************************/
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/* For Infra VIO_DBG */
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#define INFRA_VIO_DBG_MSTID 0x0000FFFF
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#define INFRA_VIO_DBG_MSTID_START_BIT 0
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#define INFRA_VIO_DBG_DMNID 0x003F0000
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#define INFRA_VIO_DBG_DMNID_START_BIT 16
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#define INFRA_VIO_DBG_W_VIO 0x00400000
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#define INFRA_VIO_DBG_W_VIO_START_BIT 22
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#define INFRA_VIO_DBG_R_VIO 0x00800000
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#define INFRA_VIO_DBG_R_VIO_START_BIT 23
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#define INFRA_VIO_ADDR_HIGH 0x0F000000
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#define INFRA_VIO_ADDR_HIGH_START_BIT 24
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/* For SRAMROM VIO */
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#define SRAMROM_SEC_VIO_ID_MASK 0x00FFFF00
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#define SRAMROM_SEC_VIO_ID_SHIFT 8
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#define SRAMROM_SEC_VIO_DOMAIN_MASK 0x0F000000
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#define SRAMROM_SEC_VIO_DOMAIN_SHIFT 24
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#define SRAMROM_SEC_VIO_RW_MASK 0x80000000
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#define SRAMROM_SEC_VIO_RW_SHIFT 31
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/* For DEVAPC PD */
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#define PD_VIO_MASK_OFFSET 0x0
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#define PD_VIO_STA_OFFSET 0x400
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#define PD_VIO_DBG0_OFFSET 0x900
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#define PD_VIO_DBG1_OFFSET 0x904
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#define PD_APC_CON_OFFSET 0xF00
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#define PD_SHIFT_STA_OFFSET 0xF10
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#define PD_SHIFT_SEL_OFFSET 0xF14
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#define PD_SHIFT_CON_OFFSET 0xF20
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#endif /* __DEVAPC_MT6785_H__ */
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