threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
195 lines
5.2 KiB
C
195 lines
5.2 KiB
C
/*
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* Copyright (c) 2017 MediaTek Inc.
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* Author: Mars.Cheng <mars.cheng@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/printk.h>
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#include <linux/module.h>
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#include <asm/cacheflush.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/irqreturn.h>
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#include <linux/platform_device.h>
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#include <linux/bug.h>
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#include <mt-plat/aee.h>
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void __iomem *parity_debug_base;
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unsigned int l2_err_status_offset;
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unsigned int l3_err_status_offset;
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#define PRINT_L2C_DBG \
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"%s%s = 0x%x,%s = 0x%x,%s = 0x%x,%s = 0x%x,%s = 0x%x\n" \
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"%s = 0x%x,%s = 0x%x,%s = 0x%x,%s = 0x%x\n" \
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"%s = 0x%x,%s = 0x%x,%s = 0x%x,%s = 0x%x\n" \
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"%s = 0x%x,%s = 0x%x,%s = 0x%x,%s = 0x%x\n"
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static irqreturn_t l2c_parity_interrupt(int irq, void *dev_id)
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{
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unsigned int l2c_reg[17];
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int i;
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pr_debug(">>> L2 Parity Error!! <<<\n");
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if (l2_err_status_offset) {
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for (i = 0; i < 17; i++)
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l2c_reg[i] = readl(parity_debug_base +
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l2_err_status_offset + 4*i);
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writel(0xFF, parity_debug_base + l2_err_status_offset);
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dsb(sy);
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writel(0x0, parity_debug_base + l2_err_status_offset);
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dsb(sy);
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pr_debug(PRINT_L2C_DBG,
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"L2C parity error.\n",
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"error status", l2c_reg[0],
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"CPU0 info1", l2c_reg[1], "CPU0 info2", l2c_reg[2],
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"CPU1 info1", l2c_reg[3], "CPU1 info2", l2c_reg[4],
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"CPU2 info1", l2c_reg[5], "CPU2 info2", l2c_reg[6],
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"CPU3 info1", l2c_reg[7], "CPU3 info2", l2c_reg[8],
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"CPU4 info1", l2c_reg[9], "CPU4 info2", l2c_reg[10],
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"CPU5 info1", l2c_reg[11], "CPU5 info2", l2c_reg[12],
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"CPU6 info1", l2c_reg[13], "CPU6 info2", l2c_reg[14],
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"CPU7 info1", l2c_reg[15], "CPU7 info2", l2c_reg[16]);
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aee_kernel_exception("L2C parity Error",
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PRINT_L2C_DBG,
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"L2C parity error.\n",
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"error status", l2c_reg[0],
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"CPU0 info1", l2c_reg[1], "CPU0 info2", l2c_reg[2],
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"CPU1 info1", l2c_reg[3], "CPU1 info2", l2c_reg[4],
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"CPU2 info1", l2c_reg[5], "CPU2 info2", l2c_reg[6],
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"CPU3 info1", l2c_reg[7], "CPU3 info2", l2c_reg[8],
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"CPU4 info1", l2c_reg[9], "CPU4 info2", l2c_reg[10],
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"CPU5 info1", l2c_reg[11], "CPU5 info2", l2c_reg[12],
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"CPU6 info1", l2c_reg[13], "CPU6 info2", l2c_reg[14],
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"CPU7 info1", l2c_reg[15], "CPU7 info2", l2c_reg[16]);
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}
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#ifdef CONFIG_MTK_ENG_BUILD
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WARN_ON(1);
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#endif
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return IRQ_NONE;
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}
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static irqreturn_t l3c_parity_interrupt(int irq, void *dev_id)
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{
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pr_debug(">>> L3 Parity Error!! <<<\n");
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if (l3_err_status_offset) {
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pr_debug("%s%s = 0x%x,%s = 0x%x,%s = 0x%x,\n",
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"L2C parity error.\n", "L3 parity 1",
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readl(parity_debug_base + l3_err_status_offset),
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"L3 parity 2",
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readl(parity_debug_base + l3_err_status_offset + 4),
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"L3 parity 3",
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readl(parity_debug_base + l3_err_status_offset + 8));
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aee_kernel_exception("L3C parity Error",
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"%s%s = 0x%x,%s = 0x%x,%s = 0x%x,\n",
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"L2C parity error.\n", "L3 parity 1",
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readl(parity_debug_base + l3_err_status_offset),
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"L3 parity 2",
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readl(parity_debug_base + l3_err_status_offset + 4),
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"L3 parity 3",
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readl(parity_debug_base + l3_err_status_offset + 8));
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writel(0x1, parity_debug_base + l3_err_status_offset + 8);
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dsb(sy);
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writel(0x0, parity_debug_base + l3_err_status_offset + 8);
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dsb(sy);
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}
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#ifdef CONFIG_MTK_ENG_BUILD
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WARN_ON(1);
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#endif
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return IRQ_NONE;
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}
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static int l2c_parity_probe(struct platform_device *pdev)
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{
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int irq = -1;
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int i = 1;
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int target_all;
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const char *irq_name;
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int ret;
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parity_debug_base = of_iomap(pdev->dev.of_node, 0);
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if (!parity_debug_base)
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return -ENOMEM;
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ret = of_property_read_u32(pdev->dev.of_node, "l2_err_status_offset",
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&l2_err_status_offset);
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if (ret)
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return ret;
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ret = of_property_read_u32(pdev->dev.of_node, "l3_err_status_offset",
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&l3_err_status_offset);
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if (ret)
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return ret;
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ret = of_property_read_u32(pdev->dev.of_node, "target_all",
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&target_all);
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if (ret)
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return ret;
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/* L3C Parity */
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irq = of_irq_get(pdev->dev.of_node, 0);
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if (irq > 0)
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if (request_irq(irq, &l3c_parity_interrupt,
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IRQF_TRIGGER_NONE, "L3C_irq", 0))
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return -EIO;
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/* L2C parity */
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while ((irq = of_irq_get(pdev->dev.of_node, i)) > 0) {
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ret = of_property_read_string_index(pdev->dev.of_node,
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"interrupt-names", i, &irq_name);
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if (ret < 0)
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irq_name = "L2C_irq";
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if ((i-1) > target_all) {
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if (irq_set_affinity(irq, cpumask_of(i-1)))
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return -EIO;
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}
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if (request_irq(irq, &l2c_parity_interrupt,
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IRQF_TRIGGER_NONE, irq_name, 0))
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return -EIO;
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i++;
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}
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return 0;
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}
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static const struct of_device_id l2c_parity_of_ids[] = {
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{ .compatible = "mediatek,l2c_parity-v1", },
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{}
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};
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static struct platform_driver l2c_parity_drv = {
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.driver = {
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.name = "l2_parity",
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.bus = &platform_bus_type,
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.owner = THIS_MODULE,
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.of_match_table = l2c_parity_of_ids,
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},
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.probe = l2c_parity_probe,
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};
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static int __init l2c_parity_init(void)
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{
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return platform_driver_register(&l2c_parity_drv);
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}
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module_init(l2c_parity_init);
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