threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
398 lines
12 KiB
C
398 lines
12 KiB
C
/*
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* Copyright (C) 2019 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
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*/
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#ifndef FM_REG_UTILS_H
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#define FM_REG_UTILS_H
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/vmalloc.h>
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#include "fm_ext_api.h"
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/* SPI register address */
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#if CFG_FM_CONNAC2
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#define SYS_SPI_BASE_ADDR (0x0000)
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#else
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#define SYS_SPI_BASE_ADDR (0x6000)
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#endif
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#define SYS_SPI_STA (0x00 + SYS_SPI_BASE_ADDR)
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#define SYS_SPI_CRTL (0x04 + SYS_SPI_BASE_ADDR)
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#define SYS_SPI_DIV (0x08 + SYS_SPI_BASE_ADDR)
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#define SYS_SPI_FM_CTRL (0x0C + SYS_SPI_BASE_ADDR)
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/* control bit for SPI_STA */
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#define SYS_SPI_ADDR_CR_MASK (0x0FFF)
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#define SYS_SPI_ADDR_CR_READ (0x01 << 12)
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#define SYS_SPI_ADDR_CR_WRITE (0x00 << 12)
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#define SYS_SPI_ADDR_CR_WF1 (0x00 << 13)
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#define SYS_SPI_ADDR_CR_WF (0x01 << 13)
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#define SYS_SPI_ADDR_CR_BT (0x02 << 13)
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#define SYS_SPI_ADDR_CR_FM (0x03 << 13)
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#define SYS_SPI_ADDR_CR_GPS (0x04 << 13)
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#define SYS_SPI_ADDR_CR_TOP (0x05 << 13)
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#define SYS_SPI_STA_WF_BUSY_ADDR SYS_SPI_STA
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#define SYS_SPI_STA_WF_BUSY_MASK 0x0002
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#define SYS_SPI_STA_WF_BUSY_SHFT 1
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#define SYS_SPI_STA_BT_BUSY_ADDR SYS_SPI_STA
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#define SYS_SPI_STA_BT_BUSY_MASK 0x0004
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#define SYS_SPI_STA_BT_BUSY_SHFT 2
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#define SYS_SPI_STA_FM_BUSY_ADDR SYS_SPI_STA
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#define SYS_SPI_STA_FM_BUSY_MASK 0x0008
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#define SYS_SPI_STA_FM_BUSY_SHFT 3
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#define SYS_SPI_STA_GPS_BUSY_ADDR SYS_SPI_STA
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#define SYS_SPI_STA_GPS_BUSY_MASK 0x0010
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#define SYS_SPI_STA_GPS_BUSY_SHFT 4
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#define SYS_SPI_STA_TOP_BUSY_ADDR SYS_SPI_STA
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#define SYS_SPI_STA_TOP_BUSY_MASK 0x0020
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#define SYS_SPI_STA_TOP_BUSY_SHFT 5
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/* control bit for SPI_STA */
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#define SYS_SPI_CRTL_MASTER_EN_ADDR SYS_SPI_CRTL
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#define SYS_SPI_CRTL_MASTER_EN_MASK 0x8000
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#define SYS_SPI_CRTL_MASTER_EN_SHFT 15
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/* control bit for SPI_DIV */
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#define SYS_SPI_DIV_DIV_CNT_ADDR SYS_SPI_DIV
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#define SYS_SPI_DIV_DIV_CNT_MASK 0x00FF
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#define SYS_SPI_DIV_DIV_CNT_SHFT 0
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/* control bit for SPI_FM_CTRL */
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#define SYS_SPI_FM_CTRL_FM_RD_EXT_CNT_ADDR SYS_SPI_FM_CTRL
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#define SYS_SPI_FM_CTRL_FM_RD_EXT_CNT_MASK 0x00FF
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#define SYS_SPI_FM_CTRL_FM_RD_EXT_CNT_SHFT 0
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#define SYS_SPI_FM_CTRL_FM_RD_EXT_EN_ADDR SYS_SPI_FM_CTRL
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#define SYS_SPI_FM_CTRL_FM_RD_EXT_EN_MASK 0x8000
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#define SYS_SPI_FM_CTRL_FM_RD_EXT_EN_SHFT 15
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/* WIFI data addr & mask */
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#define SYS_SPI_WF_ADDR_ADDR (0x10 + SYS_SPI_BASE_ADDR)
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#define SYS_SPI_WF_ADDR_MASK 0xFFFF
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#define SYS_SPI_WF_ADDR_SHFT 0
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#define SYS_SPI_WF_WDAT_ADDR (0x14 + SYS_SPI_BASE_ADDR)
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#define SYS_SPI_WF_WDAT_MASK 0xFFFFFFFF
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#define SYS_SPI_WF_WDAT_SHFT 0
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#define SYS_SPI_WF_RDAT_ADDR (0x18 + SYS_SPI_BASE_ADDR)
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#define SYS_SPI_WF_RDAT_MASK 0xFFFFFFFF
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#define SYS_SPI_WF_RDAT_SHFT 0
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/* BT data addr & mask */
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#define SYS_SPI_BT_ADDR_ADDR (0x20 + SYS_SPI_BASE_ADDR)
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#define SYS_SPI_BT_ADDR_MASK 0xFFFF
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#define SYS_SPI_BT_ADDR_SHFT 0
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#define SYS_SPI_BT_WDAT_ADDR (0x24 + SYS_SPI_BASE_ADDR)
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#define SYS_SPI_BT_WDAT_MASK 0xFF
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#define SYS_SPI_BT_WDAT_SHFT 0
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#define SYS_SPI_BT_RDAT_ADDR (0x28 + SYS_SPI_BASE_ADDR)
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#define SYS_SPI_BT_RDAT_MASK 0xFF
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#define SYS_SPI_BT_RDAT_SHFT 0
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/* FM data addr & mask */
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#define SYS_SPI_FM_ADDR_ADDR (0x30 + SYS_SPI_BASE_ADDR)
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#define SYS_SPI_FM_ADDR_MASK 0xFFFF
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#define SYS_SPI_FM_ADDR_SHFT 0
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#define SYS_SPI_FM_WDAT_ADDR (0x34 + SYS_SPI_BASE_ADDR)
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#define SYS_SPI_FM_WDAT_MASK 0xFFFF
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#define SYS_SPI_FM_WDAT_SHFT 0
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#define SYS_SPI_FM_RDAT_ADDR (0x38 + SYS_SPI_BASE_ADDR)
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#define SYS_SPI_FM_RDAT_MASK 0xFFFF
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#define SYS_SPI_FM_RDAT_SHFT 0
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/* GPS data addr & mask */
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#define SYS_SPI_GPS_ADDR_ADDR (0x40 + SYS_SPI_BASE_ADDR)
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#define SYS_SPI_GPS_ADDR_MASK 0xFFFF
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#define SYS_SPI_GPS_ADDR_SHFT 0
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#define SYS_SPI_GPS_WDAT_ADDR (0x44 + SYS_SPI_BASE_ADDR)
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#define SYS_SPI_GPS_WDAT_MASK 0xFFFFFFFF
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#define SYS_SPI_GPS_WDAT_SHFT 0
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#define SYS_SPI_GPS_RDAT_ADDR (0x48 + SYS_SPI_BASE_ADDR)
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#define SYS_SPI_GPS_RDAT_MASK 0xFFFFFFFF
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#define SYS_SPI_GPS_RDAT_SHFT 0
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/* TOP data addr & mask */
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#define SYS_SPI_TOP_ADDR_ADDR (0x50 + SYS_SPI_BASE_ADDR)
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#define SYS_SPI_TOP_ADDR_MASK 0xFFFF
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#define SYS_SPI_TOP_ADDR_SHFT 0
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#define SYS_SPI_TOP_WDAT_ADDR (0x54 + SYS_SPI_BASE_ADDR)
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#define SYS_SPI_TOP_WDAT_MASK 0xFFFFFFFF
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#define SYS_SPI_TOP_WDAT_SHFT 0
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#define SYS_SPI_TOP_RDAT_ADDR (0x58 + SYS_SPI_BASE_ADDR)
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#define SYS_SPI_TOP_RDAT_MASK 0xFFFFFFFF
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#define SYS_SPI_TOP_RDAT_SHFT 0
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/* A-die TOP SPI registers */
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#define SYSCTL_HW_ID 0x24
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#define SYSCTL_ADIE_TOP_THADC 0xC4
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#define SYSCTL_CLK_STATUS 0xA00
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#define SYSCTL_WF_CLK_EN 0xA04
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#define SYSCTL_BT_CLK_EN 0xA08
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#define SYSCTL_GPS_CLK_EN 0xA0C
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#define SYSCTL_TOP_CLK_EN 0xA10
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#define SYSCTL_EFUSE_SIZE 32
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#define SYSCTL_Macro0_Efuse_D0 0x11C
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#define SYSCTL_Macro1_Efuse_D0 0x124
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/* FM basic-operation's opcode */
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#define FM_BOP_BASE (0x80)
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enum {
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FM_WRITE_BASIC_OP = (FM_BOP_BASE + 0x00),
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FM_UDELAY_BASIC_OP = (FM_BOP_BASE + 0x01),
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FM_RD_UNTIL_BASIC_OP = (FM_BOP_BASE + 0x02),
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FM_MODIFY_BASIC_OP = (FM_BOP_BASE + 0x03),
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FM_MSLEEP_BASIC_OP = (FM_BOP_BASE + 0x04),
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FM_WRITE_SPI_BASIC_OP = (FM_BOP_BASE + 0x05),
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FM_RD_SPI_UNTIL_BASIC_OP = (FM_BOP_BASE + 0x06),
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FM_MODIFY_SPI_BASIC_OP = (FM_BOP_BASE + 0x07),
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FM_COPY_BY_MASK_BASIC_OP = (FM_BOP_BASE + 0x08),
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FM_MAX_BASIC_OP = (FM_BOP_BASE + 0x09)
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};
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/* FM SPI control registers */
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#define FSPI_MAS_BASE (0x80060000)
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#define FSPI_MAS_CONTROL_REG (FSPI_MAS_BASE + 0x0000)
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#define FSPI_MAS_ADDR_REG (FSPI_MAS_BASE + 0x0004)
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#define FSPI_MAS_WRDATA_REG (FSPI_MAS_BASE + 0x0008)
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#define FSPI_MAS_RDDATA_REG (FSPI_MAS_BASE + 0x000C)
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#define FSPI_MAS_CFG1_REG (FSPI_MAS_BASE + 0x0010)
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#define FSPI_MAS_CFG2_REG (FSPI_MAS_BASE + 0x0014)
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#define FSPI_MAS_MODESEL_REG (FSPI_MAS_BASE + 0x0020)
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#define FSPI_MAS_RESET_REG (FSPI_MAS_BASE + 0x0030)
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#define FSPI_MAS_DEBUG1_REG (FSPI_MAS_BASE + 0x0034)
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#define FSPI_MAS_DEBUG2_REG (FSPI_MAS_BASE + 0x0038)
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#define FSPI_MAS_DEBUG3_REG (FSPI_MAS_BASE + 0x003C)
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#define FSPI_MAS_DEBUG4_REG (FSPI_MAS_BASE + 0x0040)
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#define FSPI_MAS_DEBUG5_REG (FSPI_MAS_BASE + 0x0048)
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/* FM Main Control Register */
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#define FM_MAIN_CTRL_TUNE (0x0001)
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#define FM_MAIN_CTRL_SEEK (0x0002)
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#define FM_MAIN_CTRL_SCAN (0x0004)
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#define FM_MAIN_CTRL_DSP_INIT (0x0008)
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#define FM_MAIN_CTRL_SCAN_CQI (0x0008)
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#define FM_MAIN_CTRL_RDS (0x0010)
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#define FM_MAIN_CTRL_DCOC (0x0020)
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#define FM_MAIN_CTRL_MUTE (0x0040)
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#define FM_MAIN_CTRL_IQCAL (0x0080)
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#define FM_MAIN_CTRL_RAMPDOWN (0x0100)
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#define FM_MAIN_CTRL_MEM_FLUSH (0x0200)
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#define FM_MAIN_CTRL_MASK (0x0Fff)
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/* RDS control registers */
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#define FM_RDS_BASE (0x0)
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#define RDS_INFO_REG (FM_RDS_BASE + 0x81)
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#define RDS_CRC_CORR_CNT 0x001E
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#define RDS_CRC_INFO 0x0001
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#define RDS_DATA_REG (FM_RDS_BASE + 0x82)
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#define SCAN_BUFF_LEN 0xF
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#define RDS_SIN_REG (FM_RDS_BASE + 0x85)
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#define RDS_COS_REG (FM_RDS_BASE + 0x86)
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#define RDS_FIFO_STATUS0 (FM_RDS_BASE + 0x87)
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#define RDS_POINTER (FM_RDS_BASE + 0xF0)
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/* RDS Interrupt Status Register */
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#define RDS_INTR_THRE (0x0001)
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#define RDS_INTR_TO (0x0002)
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#define RDS_INTR_FULL (0x0004)
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#define RDS_INTR_MASK (0x0007)
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#define RDS_TX_INTR_MASK (0x0070)
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#define RDS_TX_INTR_EMPTY (0x0010)
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#define RDS_TX_INTR_LOW (0x0020)
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#define RDS_TX_INTR_FULL (0x0040)
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#define RDS_TX_INTR_EMPTY_MASK (0x0001)
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#define RDS_TX_INTR_LOW_MASK (0x0002)
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#define RDS_TX_INTR_FULL_MASK (0x0004)
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/* RDS Data CRC Offset Register */
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#define RDS_DCO_FIFO_OFST (0x007C)
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#define RDS_DCO_FIFO_OFST_SHFT 2
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/* Parameter for RDS */
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/* total 12 groups */
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#define RDS_RX_FIFO_CNT (12)
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/* delay 1us between each register read */
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#define RDS_READ_DELAY (1)
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#define RDS_GROUP_READ_DELAY (85)
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#define FIFO_LEN (48)
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/* Parameter for DSP download */
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#define OFFSET_REG 0x91
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#define CONTROL_REG 0x90
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#define DATA_REG 0x92
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#define FM_SOFTMUTE_TUNE_CQI_SIZE 0x16
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#define FM_SPI_COUNT_LIMIT 100000
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#define FM_BUFFER_SIZE (2048)
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#define FM_HDR_SIZE (4)
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/* FM main registers */
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enum {
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FM_MAIN_MCLKDESENSE = 0x38,
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FM_MAIN_CG1_CTRL = 0x60,
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FM_MAIN_CG2_CTRL = 0x61,
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FM_MAIN_HWVER = 0x62,
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FM_MAIN_CTRL = 0x63,
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FM_MAIN_EN1 = 0x64,
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FM_CHANNEL_SET = 0x65,
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FM_MAIN_CFG1 = 0x66,
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FM_MAIN_CFG2 = 0x67,
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FM_MAIN_CFG3 = 0x68,
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FM_MAIN_INTR = 0x69,
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FM_MAIN_INTRMASK = 0x6A,
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FM_MAIN_EXTINTRMASK = 0x6B,
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FM_RSSI_IND = 0x6C,
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FM_RSSI_TH = 0x6D,
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FM_MAIN_RESET = 0x6E,
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FM_MAIN_CHANDETSTAT = 0x6F,
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FM_MAIN_IQCOMP1 = 0x70,
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FM_MAIN_IQCOMP2 = 0x71,
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FM_MAIN_IQCOMP3 = 0x72,
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FM_MAIN_IQCOMP4 = 0x73,
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FM_MAIN_RXCALSTAT1 = 0x74,
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FM_MAIN_RXCALSTAT2 = 0x75,
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FM_MAIN_RXCALSTAT3 = 0x76,
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FM_MAIN_MCLKDESENSE2 = 0x77,
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FM_MAIN_MCLKDESENSE3 = 0x78,
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FM_MAIN_CHNLSCAN_CTRL = 0x79,
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FM_MAIN_CHNLSCAN_STAT = 0x7a,
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FM_MAIN_CHNLSCAN_STAT2 = 0x7b,
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FM_RDS_CFG0 = 0x80,
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FM_RDS_INFO = 0x81,
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FM_RDS_DATA_REG = 0x82,
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FM_RDS_GOODBK_CNT = 0x83,
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FM_RDS_BADBK_CNT = 0x84,
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FM_RDS_PWDI = 0x85,
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FM_RDS_PWDQ = 0x86,
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FM_RDS_FIFO_STATUS0 = 0x87,
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FM_FT_CON9 = 0x8F,
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FM_DSP_PATCH_CTRL = 0x90,
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FM_DSP_PATCH_OFFSET = 0x91,
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FM_DSP_PATCH_DATA = 0x92,
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FM_DSP_MEM_CTRL4 = 0x93,
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FM_MAIN_PGSEL = 0x9f,
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FM_ADDR_PAMD = 0xB4,
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FM_RDS_BDGRP_ABD_CTRL_REG = 0xB6,
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FM_RDS_POINTER = 0xF0,
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};
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/* FM Main Interrupt Register */
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enum {
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FM_INTR_STC_DONE = 0x0001,
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FM_INTR_IQCAL_DONE = 0x0002,
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FM_INTR_DESENSE_HIT = 0x0004,
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FM_INTR_CHNL_CHG = 0x0008,
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FM_INTR_SW_INTR = 0x0010,
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FM_INTR_RDS = 0x0020,
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FM_INTR_CQI = 0x0021,
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FM_INTR_MASK = 0x003f
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};
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enum {
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DSP_ROM = 0,
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DSP_PATCH,
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DSP_COEFF,
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DSP_HWCOEFF
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};
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struct fm_wcn_reg_info {
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phys_addr_t spi_phy_addr;
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void __iomem *spi_vir_addr;
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unsigned int spi_size;
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phys_addr_t top_phy_addr;
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void __iomem *top_vir_addr;
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unsigned int top_size;
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phys_addr_t mcu_phy_addr;
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void __iomem *mcu_vir_addr;
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unsigned int mcu_size;
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};
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struct fm_spi_interface {
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struct fm_wcn_reg_info info;
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void (*spi_read)(struct fm_spi_interface *si, unsigned int addr, unsigned int *val);
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void (*spi_write)(struct fm_spi_interface *si, unsigned int addr, unsigned int val);
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void (*host_read)(struct fm_spi_interface *si, unsigned int addr, unsigned int *val);
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void (*host_write)(struct fm_spi_interface *si, unsigned int addr, unsigned int val);
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int (*sys_spi_read)(struct fm_spi_interface *si, unsigned int subsystem,
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unsigned int addr, unsigned int *data);
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int (*sys_spi_write)(struct fm_spi_interface *si, unsigned int subsystem,
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unsigned int addr, unsigned int data);
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bool (*set_own)(void);
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bool (*clr_own)(void);
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};
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struct fm_wcn_reg_ops {
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struct fm_ext_interface ei;
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struct fm_spi_interface si;
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unsigned char rx_buf[FM_BUFFER_SIZE];
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unsigned int rx_len;
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struct fm_lock *tx_lock;
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struct fm_lock *own_lock;
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};
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struct fm_full_cqi {
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unsigned short ch;
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unsigned short rssi;
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unsigned short pamd;
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unsigned short pr;
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unsigned short fpamd;
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unsigned short mr;
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unsigned short atdc;
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unsigned short prx;
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unsigned short atdev;
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unsigned short smg; /* soft-mute gain */
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unsigned short drssi; /* delta rssi */
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};
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/* FM interface */
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void fw_spi_read(unsigned char addr, unsigned short *data);
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void fw_spi_write(unsigned char addr, unsigned short data);
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void fw_bop_udelay(unsigned int usec);
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void fw_bop_rd_until(unsigned char addr, unsigned short mask,
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unsigned short value);
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void fw_bop_copy_by_mask(unsigned char src, unsigned char dst,
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unsigned short mask_and);
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void fw_bop_modify(unsigned char addr, unsigned short mask_and,
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unsigned short mask_or);
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void fw_bop_spi_rd_until(unsigned char subsys, unsigned short addr,
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unsigned int mask, unsigned int value);
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void fw_bop_spi_modify(unsigned char subsys, unsigned short addr,
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unsigned int mask_and, unsigned int mask_or);
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extern struct fm_wcn_reg_ops fm_wcn_ops;
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extern unsigned char *cmd_buf;
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extern struct fm_lock *cmd_buf_lock;
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extern struct fm_res_ctx *fm_res;
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#endif /* FM_REG_UTILS_H */
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