threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
91 lines
3.9 KiB
C
91 lines
3.9 KiB
C
/*
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* Copyright (C) 2015 MediaTek Inc.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __CMDQ_REG_H__
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#define __CMDQ_REG_H__
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#include <mt-plat/sync_write.h>
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#include <linux/io.h>
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#include "cmdq_core.h"
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#include "cmdq_device.h"
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#define MMSYS_CONFIG_BASE cmdq_dev_get_module_base_VA_MMSYS_CONFIG()
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#define GCE_BASE_PA cmdq_dev_get_module_base_PA_GCE()
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#define GCE_BASE_VA cmdq_dev_get_module_base_VA_GCE()
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#define CMDQ_CORE_WARM_RESET (GCE_BASE_VA + 0x000)
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#define CMDQ_CURR_IRQ_STATUS (GCE_BASE_VA + 0x010)
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#define CMDQ_SECURE_IRQ_STATUS (GCE_BASE_VA + 0x014)
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#define CMDQ_CURR_LOADED_THR (GCE_BASE_VA + 0x018)
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#define CMDQ_THR_SLOT_CYCLES (GCE_BASE_VA + 0x030)
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#define CMDQ_THR_EXEC_CYCLES (GCE_BASE_VA + 0x034)
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#define CMDQ_THR_TIMEOUT_TIMER (GCE_BASE_VA + 0x038)
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#define CMDQ_BUS_CONTROL_TYPE (GCE_BASE_VA + 0x040)
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#define CMDQ_CURR_INST_ABORT (GCE_BASE_VA + 0x020)
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#define CMDQ_CURR_REG_ABORT (GCE_BASE_VA + 0x050)
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#define CMDQ_SECURITY_STA(id) (GCE_BASE_VA + (0x030 * id) + 0x024)
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#define CMDQ_SECURITY_SET(id) (GCE_BASE_VA + (0x030 * id) + 0x028)
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#define CMDQ_SECURITY_CLR(id) (GCE_BASE_VA + (0x030 * id) + 0x02C)
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#define CMDQ_SYNC_TOKEN_ID (GCE_BASE_VA + 0x060)
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#define CMDQ_SYNC_TOKEN_VAL (GCE_BASE_VA + 0x064)
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#define CMDQ_SYNC_TOKEN_UPD (GCE_BASE_VA + 0x068)
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#define CMDQ_PREFETCH_GSIZE (GCE_BASE_VA + 0x0C0)
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#define CMDQ_GPR_R32(id) (GCE_BASE_VA + (0x004 * id) + 0x80)
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#define CMDQ_GPR_R32_PA(id) (GCE_BASE_PA + (0x004 * id) + 0x80)
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#define CMDQ_THR_WARM_RESET(id) (GCE_BASE_VA + (0x080 * id) + 0x100)
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#define CMDQ_THR_ENABLE_TASK(id) (GCE_BASE_VA + (0x080 * id) + 0x104)
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#define CMDQ_THR_SUSPEND_TASK(id) (GCE_BASE_VA + (0x080 * id) + 0x108)
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#define CMDQ_THR_CURR_STATUS(id) (GCE_BASE_VA + (0x080 * id) + 0x10C)
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#define CMDQ_THR_IRQ_STATUS(id) (GCE_BASE_VA + (0x080 * id) + 0x110)
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#define CMDQ_THR_IRQ_ENABLE(id) (GCE_BASE_VA + (0x080 * id) + 0x114)
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#define CMDQ_THR_SECURITY(id) (GCE_BASE_VA + (0x080 * id) + 0x118)
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#define CMDQ_THR_CURR_ADDR(id) (GCE_BASE_VA + (0x080 * id) + 0x120)
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#define CMDQ_THR_END_ADDR(id) (GCE_BASE_VA + (0x080 * id) + 0x124)
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#define CMDQ_THR_EXEC_CNT(id) (GCE_BASE_VA + (0x080 * id) + 0x128)
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#define CMDQ_THR_WAIT_TOKEN(id) (GCE_BASE_VA + (0x080 * id) + 0x130)
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#define CMDQ_THR_CFG(id) (GCE_BASE_VA + (0x080 * id) + 0x140)
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#define CMDQ_THR_PREFETCH(id) (GCE_BASE_VA + (0x080 * id) + 0x144)
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#define CMDQ_THR_INST_CYCLES(id) (GCE_BASE_VA + (0x080 * id) + 0x150)
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#define CMDQ_THR_INST_THRESX(id) (GCE_BASE_VA + (0x080 * id) + 0x154)
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#define CMDQ_THR_EXEC_CNT_PA(id) (GCE_BASE_PA + (0x080 * id) + 0x128)
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#define CMDQ_GCE_END_ADDR_PA (GCE_BASE_PA + 0xC00)
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#define CMDQ_THR_FIX_END_ADDR(id) (CMDQ_GCE_END_ADDR_PA | (id << 4))
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#define CMDQ_IS_END_ADDR(addr) ((addr & CMDQ_GCE_END_ADDR_PA) == \
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CMDQ_GCE_END_ADDR_PA)
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#define CMDQ_APXGPT2_COUNT (cmdq_dev_get_APXGPT2_count())
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#define CMDQ_REG_GET32(addr) (readl((void *)addr) & 0xFFFFFFFF)
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#define CMDQ_REG_GET16(addr) (readl((void *)addr) & 0x0000FFFF)
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#define CMDQ_REG_GET64_GPR_PX(id) cmdq_core_get_GPR64(id)
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#define CMDQ_REG_SET64_GPR_PX(id, value) cmdq_core_set_GPR64(id, value)
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#define CMDQ_GET_GPR_PX2RX_LOW(id) ((id & 0xf) * 2)
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#define CMDQ_GET_GPR_PX2RX_HIGH(id) ((id & 0xf) * 2 + 1)
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#define CMDQ_REG_SET32(addr, val) mt_reg_sync_writel(val, (addr))
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#endif /* __CMDQ_REG_H__ */
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