threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
118 lines
2.3 KiB
C
118 lines
2.3 KiB
C
/*
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* Copyright (C) 2017 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
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*/
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/**
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* @file mtk_gpu_bw
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* @brief Driver for GPU BW Prediction
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*/
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#include <linux/pm_qos.h>
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#include <v1/sspm_ipi.h>
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#include <sspm_ipi_pin.h>
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#include <helio-dvfsrc-ipi.h>
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#include "mtk_gpufreq_core.h"
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#include "mtk_gpu_bw.h"
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static unsigned int g_cur_request_bw;
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static struct pm_qos_request gpu_qos_request;
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#ifdef CONFIG_MTK_QOS_SUPPORT
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void mt_gpu_bw_toggle(int i32Restore)
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{
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if (i32Restore) /* powered on */
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pm_qos_update_request(&gpu_qos_request, g_cur_request_bw);
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else
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pm_qos_update_request(&gpu_qos_request, 0);
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}
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uint32_t gpu_bw_pull;
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void mt_gpu_bw_qos_vcore(unsigned int ui32BW)
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{
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g_cur_request_bw = ui32BW + gpu_bw_pull;
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pm_qos_update_request(&gpu_qos_request, g_cur_request_bw);
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}
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EXPORT_SYMBOL(mt_gpu_bw_qos_vcore);
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static int mt_gpu_bw_ap2sspm(unsigned int eCMD, int type)
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{
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struct qos_ipi_data qos_d;
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int md32Ret = -1;
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int apDebug = -1;
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qos_d.cmd = eCMD;
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apDebug = sspm_ipi_send_sync(IPI_ID_QOS, IPI_OPT_POLLING,
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&qos_d, 1, &md32Ret, 1);
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if (apDebug < 0 || md32Ret < 0) {
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dump_stack();
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if (apDebug < 0)
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gpufreq_pr_debug("%s: AP side err (%d)\n",
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__func__, apDebug);
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if (md32Ret < 0)
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gpufreq_pr_debug("%s: SSPM err (%d)\n",
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__func__, md32Ret);
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md32Ret = -1;
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}
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return md32Ret;
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}
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unsigned int mt_gpu_bw_get_BW(int type)
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{
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unsigned int ret;
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ret = mt_gpu_bw_ap2sspm(QOS_IPI_GET_GPU_BW, type);
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return ret;
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}
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EXPORT_SYMBOL(mt_gpu_bw_get_BW);
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void mt_gpu_bw_init(void)
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{
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pm_qos_add_request(&gpu_qos_request,
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PM_QOS_GPU_MEMORY_BANDWIDTH, PM_QOS_DEFAULT_VALUE);
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}
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module_param(gpu_bw_pull, uint, 0644);
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#else /* do nothing function if QOS is disabled */
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void mt_gpu_bw_toggle(int i32Restore)
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{
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;
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}
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void mt_gpu_bw_qos_vcore(unsigned int ui32BW)
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{
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;
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}
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EXPORT_SYMBOL(mt_gpu_bw_qos_vcore);
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unsigned int mt_gpu_bw_get_BW(int type)
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{
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return -1;
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}
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EXPORT_SYMBOL(mt_gpu_bw_get_BW);
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void mt_gpu_bw_init(void)
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{
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;
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}
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#endif
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