threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
69 lines
2.4 KiB
C
69 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2019 MediaTek Inc.
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* Author: Argus Lin <argus.lin@mediatek.com>
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*/
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#ifndef _REG_ACCDET_H_
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#define _REG_ACCDET_H_
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/*************Register Bit Define*************/
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/* AUDENC_ANA_CON16: */
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#define RG_AUD_MICBIAS1_LOWP_EN (1<<PMIC_RG_AUDMICBIAS1LOWPEN_SHIFT)
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/* AUDENC_ANA_CON18: */
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#define RG_ACCDET_MODE_ANA11_MODE1 (0x000F)
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#define RG_ACCDET_MODE_ANA11_MODE2 (0x008F)
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#define RG_ACCDET_MODE_ANA11_MODE6 (0x008F)
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/* ------Register_AUXADC_REG Bit Define------ */
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/* AUXADC_ADC5: Auxadc CH5 read data */
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#define AUXADC_DATA_RDY_CH5 (1<<15)
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#define AUXADC_DATA_PROCEED_CH5 (0<<15)
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#define AUXADC_DATA_MASK (0x0FFF)
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/* AUXADC_RQST0_SET: Auxadc CH5 request, relevant 0x07EC */
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#define AUXADC_RQST_CH5_SET (1<<5)
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/* AUXADC_RQST0_CLR: Auxadc CH5 request, relevant 0x07EC */
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#define AUXADC_RQST_CH5_CLR (1<<5)
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/* -----Register_EFUSE_REG Bit Define-------- */
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#define ACCDET_CALI_MASK0 (0xFF)
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#define ACCDET_CALI_MASK1 (0xFF<<8)
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#define ACCDET_CALI_MASK2 (0xFF)
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#define ACCDET_CALI_MASK3 (0xFF<<8)
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#define ACCDET_CALI_MASK4 (0xFF)
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/* -----Register_ACCDET_REG Bit Define------- */
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#define ACCDET_EINT1_IRQ_CLR_B11 (0x01<<PMIC_ACCDET_EINT1_IRQ_CLR_SHIFT)
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#define ACCDET_EINT0_IRQ_CLR_B10 (0x01<<PMIC_ACCDET_EINT0_IRQ_CLR_SHIFT)
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#define ACCDET_EINT_IRQ_CLR_B10_11 (0x03<<PMIC_ACCDET_EINT0_IRQ_CLR_SHIFT)
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#define ACCDET_IRQ_CLR_B8 (0x01<<PMIC_ACCDET_IRQ_CLR_SHIFT)
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#define ACCDET_EINT1_IRQ_B3 (0x01<<PMIC_ACCDET_EINT1_IRQ_SHIFT)
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#define ACCDET_EINT0_IRQ_B2 (0x01<<PMIC_ACCDET_EINT0_IRQ_SHIFT)
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#define ACCDET_EINT_IRQ_B2_B3 (0x03<<PMIC_ACCDET_EINT0_IRQ_SHIFT)
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#define ACCDET_IRQ_B0 (0x01<<PMIC_ACCDET_IRQ_SHIFT)
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/* ACCDET_CON25: RO, accdet FSM state,etc.*/
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#define ACCDET_STATE_MEM_IN_OFFSET (PMIC_ACCDET_MEM_IN_SHIFT)
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#define ACCDET_STATE_AB_MASK (0x03)
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#define ACCDET_STATE_AB_00 (0x00)
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#define ACCDET_STATE_AB_01 (0x01)
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#define ACCDET_STATE_AB_10 (0x02)
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#define ACCDET_STATE_AB_11 (0x03)
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/* ACCDET_CON19 */
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#define ACCDET_EINT0_STABLE_VAL ((1<<PMIC_ACCDET_DA_STABLE_SHIFT) | \
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(1<<PMIC_ACCDET_EINT0_EN_STABLE_SHIFT) | \
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(1<<PMIC_ACCDET_EINT0_CMPEN_STABLE_SHIFT) | \
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(1<<PMIC_ACCDET_EINT0_CEN_STABLE_SHIFT))
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#define ACCDET_EINT1_STABLE_VAL ((1<<PMIC_ACCDET_DA_STABLE_SHIFT) | \
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(1<<PMIC_ACCDET_EINT1_EN_STABLE_SHIFT) | \
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(1<<PMIC_ACCDET_EINT1_CMPEN_STABLE_SHIFT) | \
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(1<<PMIC_ACCDET_EINT1_CEN_STABLE_SHIFT))
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#endif/* end _REG_ACCDET_H_ */
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