threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
63 lines
1.9 KiB
C
63 lines
1.9 KiB
C
/*
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* Driver for the Auvitek USB bridge
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*
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* Copyright (c) 2008 Steven Toth <stoth@linuxtv.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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*
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* GNU General Public License for more details.
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*/
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/* We'll start to rename these registers once we have a better
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* understanding of their meaning.
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*/
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#define REG_000 0x000
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#define REG_001 0x001
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#define REG_002 0x002
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#define REG_003 0x003
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#define AU0828_SENSORCTRL_100 0x100
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#define AU0828_SENSORCTRL_VBI_103 0x103
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/* I2C registers */
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#define AU0828_I2C_TRIGGER_200 0x200
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#define AU0828_I2C_STATUS_201 0x201
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#define AU0828_I2C_CLK_DIVIDER_202 0x202
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#define AU0828_I2C_DEST_ADDR_203 0x203
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#define AU0828_I2C_WRITE_FIFO_205 0x205
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#define AU0828_I2C_READ_FIFO_209 0x209
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#define AU0828_I2C_MULTIBYTE_MODE_2FF 0x2ff
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/* Audio registers */
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#define AU0828_AUDIOCTRL_50C 0x50C
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#define REG_600 0x600
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/*********************************************************************/
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/* Here are constants for values associated with the above registers */
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/* I2C Trigger (Reg 0x200) */
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#define AU0828_I2C_TRIGGER_WRITE 0x01
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#define AU0828_I2C_TRIGGER_READ 0x20
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#define AU0828_I2C_TRIGGER_HOLD 0x40
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/* I2C Status (Reg 0x201) */
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#define AU0828_I2C_STATUS_READ_DONE 0x01
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#define AU0828_I2C_STATUS_NO_READ_ACK 0x02
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#define AU0828_I2C_STATUS_WRITE_DONE 0x04
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#define AU0828_I2C_STATUS_NO_WRITE_ACK 0x08
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#define AU0828_I2C_STATUS_BUSY 0x10
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/* I2C Clock Divider (Reg 0x202) */
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#define AU0828_I2C_CLK_250KHZ 0x07
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#define AU0828_I2C_CLK_100KHZ 0x14
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#define AU0828_I2C_CLK_30KHZ 0x40
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#define AU0828_I2C_CLK_20KHZ 0x60
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