threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
61 lines
2.0 KiB
C
61 lines
2.0 KiB
C
/*
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* Register definition file for Samsung MFC V7.x Interface (FIMV) driver
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*
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* Copyright (c) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _REGS_MFC_V7_H
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#define _REGS_MFC_V7_H
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#include "regs-mfc-v6.h"
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/* Additional features of v7 */
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#define S5P_FIMV_CODEC_VP8_ENC_V7 25
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/* Additional registers for v7 */
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#define S5P_FIMV_E_SOURCE_FIRST_ADDR_V7 0xf9e0
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#define S5P_FIMV_E_SOURCE_SECOND_ADDR_V7 0xf9e4
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#define S5P_FIMV_E_SOURCE_THIRD_ADDR_V7 0xf9e8
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#define S5P_FIMV_E_SOURCE_FIRST_STRIDE_V7 0xf9ec
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#define S5P_FIMV_E_SOURCE_SECOND_STRIDE_V7 0xf9f0
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#define S5P_FIMV_E_SOURCE_THIRD_STRIDE_V7 0xf9f4
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#define S5P_FIMV_E_ENCODED_SOURCE_FIRST_ADDR_V7 0xfa70
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#define S5P_FIMV_E_ENCODED_SOURCE_SECOND_ADDR_V7 0xfa74
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#define S5P_FIMV_E_VP8_OPTIONS_V7 0xfdb0
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#define S5P_FIMV_E_VP8_FILTER_OPTIONS_V7 0xfdb4
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#define S5P_FIMV_E_VP8_GOLDEN_FRAME_OPTION_V7 0xfdb8
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#define S5P_FIMV_E_VP8_NUM_T_LAYER_V7 0xfdc4
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/* MFCv7 variant defines */
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#define MAX_FW_SIZE_V7 (SZ_512K) /* 512KB */
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#define MAX_CPB_SIZE_V7 (3 * SZ_1M) /* 3MB */
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#define MFC_VERSION_V7 0x72
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#define MFC_NUM_PORTS_V7 1
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#define MFC_LUMA_PAD_BYTES_V7 256
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#define MFC_CHROMA_PAD_BYTES_V7 128
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/* MFCv7 Context buffer sizes */
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#define MFC_CTX_BUF_SIZE_V7 (30 * SZ_1K) /* 30KB */
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#define MFC_H264_DEC_CTX_BUF_SIZE_V7 (2 * SZ_1M) /* 2MB */
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#define MFC_OTHER_DEC_CTX_BUF_SIZE_V7 (20 * SZ_1K) /* 20KB */
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#define MFC_H264_ENC_CTX_BUF_SIZE_V7 (100 * SZ_1K) /* 100KB */
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#define MFC_OTHER_ENC_CTX_BUF_SIZE_V7 (10 * SZ_1K) /* 10KB */
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/* Buffer size defines */
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#define S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_DEC_V7(w, h) \
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(SZ_1M + ((w) * 144) + (8192 * (h)) + 49216)
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#define S5P_FIMV_SCRATCH_BUF_SIZE_VP8_ENC_V7(w, h) \
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(((w) * 48) + 8192 + ((((w) + 1) / 2) * 128) + 144 + \
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((((((w) * 16) * ((h) * 16)) * 3) / 2) * 4))
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#endif /*_REGS_MFC_V7_H*/
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