threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
58 lines
1.8 KiB
C
58 lines
1.8 KiB
C
/*
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* NETjet common header file
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*
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* Author Karsten Keil
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* based on work of Matt Henderson and Daniel Potts,
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* Traverse Technologies P/L www.traverse.com.au
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*
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* Copyright 2009 by Karsten Keil <keil@isdn4linux.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#define NJ_CTRL 0x00
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#define NJ_DMACTRL 0x01
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#define NJ_AUXCTRL 0x02
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#define NJ_AUXDATA 0x03
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#define NJ_IRQMASK0 0x04
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#define NJ_IRQMASK1 0x05
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#define NJ_IRQSTAT0 0x06
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#define NJ_IRQSTAT1 0x07
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#define NJ_DMA_READ_START 0x08
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#define NJ_DMA_READ_IRQ 0x0c
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#define NJ_DMA_READ_END 0x10
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#define NJ_DMA_READ_ADR 0x14
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#define NJ_DMA_WRITE_START 0x18
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#define NJ_DMA_WRITE_IRQ 0x1c
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#define NJ_DMA_WRITE_END 0x20
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#define NJ_DMA_WRITE_ADR 0x24
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#define NJ_PULSE_CNT 0x28
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#define NJ_ISAC_OFF 0xc0
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#define NJ_ISACIRQ 0x10
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#define NJ_IRQM0_RD_MASK 0x03
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#define NJ_IRQM0_RD_IRQ 0x01
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#define NJ_IRQM0_RD_END 0x02
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#define NJ_IRQM0_WR_MASK 0x0c
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#define NJ_IRQM0_WR_IRQ 0x04
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#define NJ_IRQM0_WR_END 0x08
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/* one page here is no need to be smaller */
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#define NJ_DMA_SIZE 4096
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/* 2 * 64 byte is a compromise between IRQ count and latency */
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#define NJ_DMA_RXSIZE 128 /* 2 * 64 */
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#define NJ_DMA_TXSIZE 128 /* 2 * 64 */
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