threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
116 lines
3.5 KiB
C
116 lines
3.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __NOUVEAU_ABI16_H__
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#define __NOUVEAU_ABI16_H__
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#define ABI16_IOCTL_ARGS \
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struct drm_device *dev, void *data, struct drm_file *file_priv
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int nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS);
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int nouveau_abi16_ioctl_setparam(ABI16_IOCTL_ARGS);
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int nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS);
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int nouveau_abi16_ioctl_channel_free(ABI16_IOCTL_ARGS);
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int nouveau_abi16_ioctl_grobj_alloc(ABI16_IOCTL_ARGS);
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int nouveau_abi16_ioctl_notifierobj_alloc(ABI16_IOCTL_ARGS);
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int nouveau_abi16_ioctl_gpuobj_free(ABI16_IOCTL_ARGS);
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struct nouveau_abi16_ntfy {
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struct nvif_object object;
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struct list_head head;
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struct nvkm_mm_node *node;
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};
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struct nouveau_abi16_chan {
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struct list_head head;
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struct nouveau_channel *chan;
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struct list_head notifiers;
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struct nouveau_bo *ntfy;
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struct nvkm_vma ntfy_vma;
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struct nvkm_mm heap;
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};
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struct nouveau_abi16 {
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struct nvif_device device;
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struct list_head channels;
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u64 handles;
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};
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struct nouveau_abi16 *nouveau_abi16_get(struct drm_file *);
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int nouveau_abi16_put(struct nouveau_abi16 *, int);
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void nouveau_abi16_fini(struct nouveau_abi16 *);
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s32 nouveau_abi16_swclass(struct nouveau_drm *);
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int nouveau_abi16_usif(struct drm_file *, void *data, u32 size);
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#define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1)
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#define NOUVEAU_GEM_DOMAIN_GART (1 << 2)
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struct drm_nouveau_channel_alloc {
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uint32_t fb_ctxdma_handle;
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uint32_t tt_ctxdma_handle;
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int channel;
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uint32_t pushbuf_domains;
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/* Notifier memory */
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uint32_t notifier_handle;
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/* DRM-enforced subchannel assignments */
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struct {
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uint32_t handle;
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uint32_t grclass;
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} subchan[8];
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uint32_t nr_subchan;
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};
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struct drm_nouveau_channel_free {
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int channel;
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};
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struct drm_nouveau_grobj_alloc {
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int channel;
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uint32_t handle;
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int class;
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};
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struct drm_nouveau_notifierobj_alloc {
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uint32_t channel;
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uint32_t handle;
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uint32_t size;
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uint32_t offset;
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};
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struct drm_nouveau_gpuobj_free {
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int channel;
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uint32_t handle;
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};
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#define NOUVEAU_GETPARAM_PCI_VENDOR 3
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#define NOUVEAU_GETPARAM_PCI_DEVICE 4
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#define NOUVEAU_GETPARAM_BUS_TYPE 5
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#define NOUVEAU_GETPARAM_FB_SIZE 8
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#define NOUVEAU_GETPARAM_AGP_SIZE 9
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#define NOUVEAU_GETPARAM_CHIPSET_ID 11
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#define NOUVEAU_GETPARAM_VM_VRAM_BASE 12
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#define NOUVEAU_GETPARAM_GRAPH_UNITS 13
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#define NOUVEAU_GETPARAM_PTIMER_TIME 14
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#define NOUVEAU_GETPARAM_HAS_BO_USAGE 15
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#define NOUVEAU_GETPARAM_HAS_PAGEFLIP 16
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struct drm_nouveau_getparam {
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uint64_t param;
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uint64_t value;
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};
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struct drm_nouveau_setparam {
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uint64_t param;
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uint64_t value;
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};
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#define DRM_IOCTL_NOUVEAU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GETPARAM, struct drm_nouveau_getparam)
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#define DRM_IOCTL_NOUVEAU_SETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SETPARAM, struct drm_nouveau_setparam)
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#define DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_ALLOC, struct drm_nouveau_channel_alloc)
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#define DRM_IOCTL_NOUVEAU_CHANNEL_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_FREE, struct drm_nouveau_channel_free)
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#define DRM_IOCTL_NOUVEAU_GROBJ_ALLOC DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GROBJ_ALLOC, struct drm_nouveau_grobj_alloc)
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#define DRM_IOCTL_NOUVEAU_NOTIFIEROBJ_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_NOTIFIEROBJ_ALLOC, struct drm_nouveau_notifierobj_alloc)
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#define DRM_IOCTL_NOUVEAU_GPUOBJ_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GPUOBJ_FREE, struct drm_nouveau_gpuobj_free)
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#endif
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