threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
71 lines
2.1 KiB
C
71 lines
2.1 KiB
C
/*
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* Copyright (c) 2014, The Linux Foundation. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/bitops.h>
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#include <linux/regmap.h>
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#include <linux/export.h>
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#include "clk-regmap-divider.h"
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static inline struct clk_regmap_div *to_clk_regmap_div(struct clk_hw *hw)
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{
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return container_of(to_clk_regmap(hw), struct clk_regmap_div, clkr);
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}
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static long div_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct clk_regmap_div *divider = to_clk_regmap_div(hw);
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return divider_round_rate(hw, rate, prate, NULL, divider->width,
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CLK_DIVIDER_ROUND_CLOSEST);
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}
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static int div_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_regmap_div *divider = to_clk_regmap_div(hw);
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struct clk_regmap *clkr = ÷r->clkr;
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u32 div;
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div = divider_get_val(rate, parent_rate, NULL, divider->width,
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CLK_DIVIDER_ROUND_CLOSEST);
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return regmap_update_bits(clkr->regmap, divider->reg,
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(BIT(divider->width) - 1) << divider->shift,
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div << divider->shift);
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}
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static unsigned long div_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_regmap_div *divider = to_clk_regmap_div(hw);
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struct clk_regmap *clkr = ÷r->clkr;
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u32 div;
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regmap_read(clkr->regmap, divider->reg, &div);
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div >>= divider->shift;
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div &= BIT(divider->width) - 1;
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return divider_recalc_rate(hw, parent_rate, div, NULL,
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CLK_DIVIDER_ROUND_CLOSEST, divider->width);
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}
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const struct clk_ops clk_regmap_div_ops = {
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.round_rate = div_round_rate,
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.set_rate = div_set_rate,
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.recalc_rate = div_recalc_rate,
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};
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EXPORT_SYMBOL_GPL(clk_regmap_div_ops);
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