threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
83 lines
1.9 KiB
C
83 lines
1.9 KiB
C
/*
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* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __QCOM_CLK_ALPHA_PLL_H__
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#define __QCOM_CLK_ALPHA_PLL_H__
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#include <linux/clk-provider.h>
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#include "clk-regmap.h"
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struct pll_vco {
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unsigned long min_freq;
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unsigned long max_freq;
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u32 val;
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};
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/**
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* struct clk_alpha_pll - phase locked loop (PLL)
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* @offset: base address of registers
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* @vco_table: array of VCO settings
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* @clkr: regmap clock handle
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*/
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struct clk_alpha_pll {
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u32 offset;
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const struct pll_vco *vco_table;
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size_t num_vco;
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#define SUPPORTS_OFFLINE_REQ BIT(0)
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#define SUPPORTS_16BIT_ALPHA BIT(1)
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#define SUPPORTS_FSM_MODE BIT(2)
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u8 flags;
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struct clk_regmap clkr;
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};
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/**
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* struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
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* @offset: base address of registers
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* @width: width of post-divider
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* @clkr: regmap clock handle
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*/
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struct clk_alpha_pll_postdiv {
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u32 offset;
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u8 width;
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struct clk_regmap clkr;
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};
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struct alpha_pll_config {
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u32 l;
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u32 alpha;
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u32 config_ctl_val;
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u32 config_ctl_hi_val;
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u32 main_output_mask;
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u32 aux_output_mask;
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u32 aux2_output_mask;
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u32 early_output_mask;
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u32 pre_div_val;
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u32 pre_div_mask;
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u32 post_div_val;
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u32 post_div_mask;
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u32 vco_val;
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u32 vco_mask;
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};
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extern const struct clk_ops clk_alpha_pll_ops;
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extern const struct clk_ops clk_alpha_pll_hwfsm_ops;
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extern const struct clk_ops clk_alpha_pll_postdiv_ops;
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void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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const struct alpha_pll_config *config);
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#endif
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