threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
56 lines
1.4 KiB
C
56 lines
1.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <linux/pci.h>
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#include <linux/acpi.h>
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#include <acpi/reboot.h>
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void acpi_reboot(void)
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{
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struct acpi_generic_address *rr;
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struct pci_bus *bus0;
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u8 reset_value;
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unsigned int devfn;
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if (acpi_disabled)
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return;
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rr = &acpi_gbl_FADT.reset_register;
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/* ACPI reset register was only introduced with v2 of the FADT */
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if (acpi_gbl_FADT.header.revision < 2)
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return;
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/* Is the reset register supported? The spec says we should be
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* checking the bit width and bit offset, but Windows ignores
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* these fields */
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if (!(acpi_gbl_FADT.flags & ACPI_FADT_RESET_REGISTER))
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return;
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reset_value = acpi_gbl_FADT.reset_value;
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/* The reset register can only exist in I/O, Memory or PCI config space
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* on a device on bus 0. */
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switch (rr->space_id) {
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case ACPI_ADR_SPACE_PCI_CONFIG:
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/* The reset register can only live on bus 0. */
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bus0 = pci_find_bus(0, 0);
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if (!bus0)
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return;
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/* Form PCI device/function pair. */
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devfn = PCI_DEVFN((rr->address >> 32) & 0xffff,
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(rr->address >> 16) & 0xffff);
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printk(KERN_DEBUG "Resetting with ACPI PCI RESET_REG.");
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/* Write the value that resets us. */
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pci_bus_write_config_byte(bus0, devfn,
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(rr->address & 0xffff), reset_value);
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break;
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case ACPI_ADR_SPACE_SYSTEM_MEMORY:
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case ACPI_ADR_SPACE_SYSTEM_IO:
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printk(KERN_DEBUG "ACPI MEMORY or I/O RESET_REG.\n");
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acpi_reset();
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break;
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}
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}
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