threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
45 lines
1.1 KiB
C
45 lines
1.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* IDT Winchip specific Machine Check Exception Reporting
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* (C) Copyright 2002 Alan Cox <alan@lxorguk.ukuu.org.uk>
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*/
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <asm/processor.h>
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#include <asm/traps.h>
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#include <asm/tlbflush.h>
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#include <asm/mce.h>
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#include <asm/msr.h>
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/* Machine check handler for WinChip C6: */
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static void winchip_machine_check(struct pt_regs *regs, long error_code)
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{
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ist_enter(regs);
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pr_emerg("CPU0: Machine Check Exception.\n");
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add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
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ist_exit(regs);
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}
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/* Set up machine check reporting on the Winchip C6 series */
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void winchip_mcheck_init(struct cpuinfo_x86 *c)
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{
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u32 lo, hi;
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machine_check_vector = winchip_machine_check;
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/* Make sure the vector pointer is visible before we enable MCEs: */
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wmb();
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rdmsr(MSR_IDT_FCR1, lo, hi);
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lo |= (1<<2); /* Enable EIERRINT (int 18 MCE) */
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lo &= ~(1<<4); /* Enable MCE */
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wrmsr(MSR_IDT_FCR1, lo, hi);
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cr4_set_bits(X86_CR4_MCE);
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pr_info("Winchip machine check reporting enabled on CPU#0.\n");
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}
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