threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
69 lines
1.9 KiB
C
69 lines
1.9 KiB
C
/*
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* linux/arch/sh/boards/se/7780/irq.c
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*
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* Copyright (C) 2006,2007 Nobuhiro Iwamatsu
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*
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* Hitachi UL SolutionEngine 7780 Support.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <mach-se/mach/se7780.h>
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#define INTC_BASE 0xffd00000
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#define INTC_ICR1 (INTC_BASE+0x1c)
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/*
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* Initialize IRQ setting
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*/
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void __init init_se7780_IRQ(void)
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{
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/* enable all interrupt at FPGA */
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__raw_writew(0, FPGA_INTMSK1);
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/* mask SM501 interrupt */
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__raw_writew((__raw_readw(FPGA_INTMSK1) | 0x0002), FPGA_INTMSK1);
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/* enable all interrupt at FPGA */
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__raw_writew(0, FPGA_INTMSK2);
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/* set FPGA INTSEL register */
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/* FPGA + 0x06 */
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__raw_writew( ((IRQPIN_SM501 << IRQPOS_SM501) |
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(IRQPIN_SMC91CX << IRQPOS_SMC91CX)), FPGA_INTSEL1);
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/* FPGA + 0x08 */
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__raw_writew(((IRQPIN_EXTINT4 << IRQPOS_EXTINT4) |
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(IRQPIN_EXTINT3 << IRQPOS_EXTINT3) |
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(IRQPIN_EXTINT2 << IRQPOS_EXTINT2) |
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(IRQPIN_EXTINT1 << IRQPOS_EXTINT1)), FPGA_INTSEL2);
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/* FPGA + 0x0A */
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__raw_writew((IRQPIN_PCCPW << IRQPOS_PCCPW), FPGA_INTSEL3);
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plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-7 */
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/* ICR1: detect low level(for 2ndcut) */
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__raw_writel(0xAAAA0000, INTC_ICR1);
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/*
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* FPGA PCISEL register initialize
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*
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* CPU || SLOT1 | SLOT2 | S-ATA | USB
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* -------------------------------------
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* INTA || INTA | INTD | -- | INTB
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* -------------------------------------
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* INTB || INTB | INTA | -- | INTC
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* -------------------------------------
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* INTC || INTC | INTB | INTA | --
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* -------------------------------------
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* INTD || INTD | INTC | -- | INTA
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* -------------------------------------
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*/
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__raw_writew(0x0013, FPGA_PCI_INTSEL1);
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__raw_writew(0xE402, FPGA_PCI_INTSEL2);
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}
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