threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
58 lines
1.7 KiB
C
58 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_POWERPC_NOHASH_64_PGTABLE_64K_H
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#define _ASM_POWERPC_NOHASH_64_PGTABLE_64K_H
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#define __ARCH_USE_5LEVEL_HACK
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#include <asm-generic/pgtable-nopud.h>
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#define PTE_INDEX_SIZE 8
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#define PMD_INDEX_SIZE 10
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#define PUD_INDEX_SIZE 0
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#define PGD_INDEX_SIZE 12
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/*
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* we support 32 fragments per PTE page of 64K size
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*/
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#define PTE_FRAG_NR 32
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/*
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* We use a 2K PTE page fragment and another 2K for storing
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* real_pte_t hash index
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*/
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#define PTE_FRAG_SIZE_SHIFT 11
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#define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT)
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#ifndef __ASSEMBLY__
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#define PTE_TABLE_SIZE PTE_FRAG_SIZE
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#define PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE)
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#define PUD_TABLE_SIZE (0)
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#define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE)
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#endif /* __ASSEMBLY__ */
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#define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
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#define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
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#define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
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/* PMD_SHIFT determines what a second-level page table entry can map */
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#define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
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#define PMD_SIZE (1UL << PMD_SHIFT)
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#define PMD_MASK (~(PMD_SIZE-1))
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/* PGDIR_SHIFT determines what a third-level page table entry can map */
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#define PGDIR_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE)
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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/*
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* Bits to mask out from a PMD to get to the PTE page
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* PMDs point to PTE table fragments which are PTE_FRAG_SIZE aligned.
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*/
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#define PMD_MASKED_BITS (PTE_FRAG_SIZE - 1)
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/* Bits to mask out from a PGD/PUD to get to the PMD page */
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#define PUD_MASKED_BITS 0x1ff
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#define pgd_pte(pgd) (pud_pte(((pud_t){ pgd })))
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#define pte_pgd(pte) ((pgd_t)pte_pud(pte))
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#endif /* _ASM_POWERPC_NOHASH_64_PGTABLE_64K_H */
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