threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
43 lines
1.3 KiB
C
43 lines
1.3 KiB
C
/*
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* Common registers for PPC AES implementation
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*
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* Copyright (c) 2015 Markus Stockhausen <stockhausen@collogia.de>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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*/
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#define rKS r0 /* copy of en-/decryption key pointer */
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#define rDP r3 /* destination pointer */
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#define rSP r4 /* source pointer */
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#define rKP r5 /* pointer to en-/decryption key pointer */
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#define rRR r6 /* en-/decryption rounds */
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#define rLN r7 /* length of data to be processed */
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#define rIP r8 /* potiner to IV (CBC/CTR/XTS modes) */
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#define rKT r9 /* pointer to tweak key (XTS mode) */
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#define rT0 r11 /* pointers to en-/decryption tables */
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#define rT1 r10
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#define rD0 r9 /* data */
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#define rD1 r14
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#define rD2 r12
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#define rD3 r15
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#define rW0 r16 /* working registers */
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#define rW1 r17
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#define rW2 r18
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#define rW3 r19
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#define rW4 r20
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#define rW5 r21
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#define rW6 r22
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#define rW7 r23
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#define rI0 r24 /* IV */
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#define rI1 r25
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#define rI2 r26
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#define rI3 r27
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#define rG0 r28 /* endian reversed tweak (XTS mode) */
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#define rG1 r29
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#define rG2 r30
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#define rG3 r31
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