threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
75 lines
1.8 KiB
C
75 lines
1.8 KiB
C
/*
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* DEC I/O ASIC's counter clocksource
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*
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* Copyright (C) 2008 Yoichi Yuasa <yuasa@linux-mips.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clocksource.h>
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#include <linux/sched_clock.h>
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#include <linux/init.h>
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#include <asm/ds1287.h>
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#include <asm/time.h>
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#include <asm/dec/ioasic.h>
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#include <asm/dec/ioasic_addrs.h>
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static u64 dec_ioasic_hpt_read(struct clocksource *cs)
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{
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return ioasic_read(IO_REG_FCTR);
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}
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static struct clocksource clocksource_dec = {
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.name = "dec-ioasic",
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.read = dec_ioasic_hpt_read,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static u64 notrace dec_ioasic_read_sched_clock(void)
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{
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return ioasic_read(IO_REG_FCTR);
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}
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int __init dec_ioasic_clocksource_init(void)
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{
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unsigned int freq;
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u32 start, end;
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int i = HZ / 8;
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ds1287_timer_state();
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while (!ds1287_timer_state())
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;
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start = dec_ioasic_hpt_read(&clocksource_dec);
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while (i--)
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while (!ds1287_timer_state())
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;
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end = dec_ioasic_hpt_read(&clocksource_dec);
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freq = (end - start) * 8;
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/* An early revision of the I/O ASIC didn't have the counter. */
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if (!freq)
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return -ENXIO;
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printk(KERN_INFO "I/O ASIC clock frequency %dHz\n", freq);
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clocksource_dec.rating = 200 + freq / 10000000;
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clocksource_register_hz(&clocksource_dec, freq);
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sched_clock_register(dec_ioasic_read_sched_clock, 32, freq);
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return 0;
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}
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