threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
71 lines
2.7 KiB
C
71 lines
2.7 KiB
C
/*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
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* Copyright (C) 2013 Imagination Technologies Ltd.
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* Register definitions for Intel PIIX4 South Bridge Device.
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*/
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#ifndef __ASM_MIPS_BOARDS_PIIX4_H
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#define __ASM_MIPS_BOARDS_PIIX4_H
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/* PIRQX Route Control */
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#define PIIX4_FUNC0_PIRQRC 0x60
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#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE (1 << 7)
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#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MASK 0xf
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#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX 16
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/* SERIRQ Control */
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#define PIIX4_FUNC0_SERIRQC 0x64
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#define PIIX4_FUNC0_SERIRQC_EN (1 << 7)
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#define PIIX4_FUNC0_SERIRQC_CONT (1 << 6)
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/* Top Of Memory */
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#define PIIX4_FUNC0_TOM 0x69
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#define PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK 0xf0
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/* Deterministic Latency Control */
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#define PIIX4_FUNC0_DLC 0x82
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#define PIIX4_FUNC0_DLC_USBPR_EN (1 << 2)
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#define PIIX4_FUNC0_DLC_PASSIVE_RELEASE_EN (1 << 1)
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#define PIIX4_FUNC0_DLC_DELAYED_TRANSACTION_EN (1 << 0)
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/* General Configuration */
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#define PIIX4_FUNC0_GENCFG 0xb0
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#define PIIX4_FUNC0_GENCFG_SERIRQ (1 << 16)
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/* IDE Timing */
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#define PIIX4_FUNC1_IDETIM_PRIMARY_LO 0x40
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#define PIIX4_FUNC1_IDETIM_PRIMARY_HI 0x41
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#define PIIX4_FUNC1_IDETIM_PRIMARY_HI_IDE_DECODE_EN (1 << 7)
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#define PIIX4_FUNC1_IDETIM_SECONDARY_LO 0x42
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#define PIIX4_FUNC1_IDETIM_SECONDARY_HI 0x43
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#define PIIX4_FUNC1_IDETIM_SECONDARY_HI_IDE_DECODE_EN (1 << 7)
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/* Power Management Configuration Space */
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#define PIIX4_FUNC3_PMBA 0x40
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#define PIIX4_FUNC3_PMREGMISC 0x80
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#define PIIX4_FUNC3_PMREGMISC_EN (1 << 0)
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/* Power Management IO Space */
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#define PIIX4_FUNC3IO_PMSTS 0x00
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#define PIIX4_FUNC3IO_PMSTS_PWRBTN_STS (1 << 8)
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#define PIIX4_FUNC3IO_PMCNTRL 0x04
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#define PIIX4_FUNC3IO_PMCNTRL_SUS_EN (1 << 13)
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#define PIIX4_FUNC3IO_PMCNTRL_SUS_TYP (0x7 << 10)
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#define PIIX4_FUNC3IO_PMCNTRL_SUS_TYP_SOFF (0x0 << 10)
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#define PIIX4_FUNC3IO_PMCNTRL_SUS_TYP_STR (0x1 << 10)
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/* Data for magic special PCI cycle */
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#define PIIX4_SUSPEND_MAGIC 0x00120002
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#endif /* __ASM_MIPS_BOARDS_PIIX4_H */
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