threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
55 lines
1.5 KiB
C
55 lines
1.5 KiB
C
/*
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* Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
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* Copyright (C) 2009 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __ASM_MACH_BMIPS_DMA_COHERENCE_H
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#define __ASM_MACH_BMIPS_DMA_COHERENCE_H
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#include <asm/bmips.h>
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#include <asm/cpu-type.h>
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#include <asm/cpu.h>
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struct device;
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extern dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size);
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extern dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page);
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extern unsigned long plat_dma_addr_to_phys(struct device *dev,
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dma_addr_t dma_addr);
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static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
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size_t size, enum dma_data_direction direction)
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{
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}
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static inline int plat_dma_supported(struct device *dev, u64 mask)
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{
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/*
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* we fall back to GFP_DMA when the mask isn't all 1s,
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* so we can't guarantee allocations that must be
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* within a tighter range than GFP_DMA..
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*/
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if (mask < DMA_BIT_MASK(24))
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return 0;
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return 1;
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}
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static inline int plat_device_is_coherent(struct device *dev)
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{
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return 0;
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}
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#define plat_post_dma_flush bmips_post_dma_flush
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#endif /* __ASM_MACH_BMIPS_DMA_COHERENCE_H */
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