threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
63 lines
1.4 KiB
C
63 lines
1.4 KiB
C
/*
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* IRQ vector handles
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1995, 1996, 1997, 2003 by Ralf Baechle
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <asm/i8259.h>
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#include <asm/irq_cpu.h>
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#include <asm/irq_gt641xx.h>
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#include <asm/gt64120.h>
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#include <irq.h>
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned pending = read_c0_status() & read_c0_cause() & ST0_IM;
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int irq;
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if (pending & CAUSEF_IP2)
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gt641xx_irq_dispatch();
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else if (pending & CAUSEF_IP6) {
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irq = i8259_irq();
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if (irq < 0)
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spurious_interrupt();
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else
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do_IRQ(irq);
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} else if (pending & CAUSEF_IP3)
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do_IRQ(MIPS_CPU_IRQ_BASE + 3);
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else if (pending & CAUSEF_IP4)
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do_IRQ(MIPS_CPU_IRQ_BASE + 4);
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else if (pending & CAUSEF_IP5)
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do_IRQ(MIPS_CPU_IRQ_BASE + 5);
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else if (pending & CAUSEF_IP7)
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do_IRQ(MIPS_CPU_IRQ_BASE + 7);
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else
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spurious_interrupt();
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}
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static struct irqaction cascade = {
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.handler = no_action,
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.name = "cascade",
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.flags = IRQF_NO_THREAD,
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};
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void __init arch_init_irq(void)
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{
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mips_cpu_irq_init();
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gt641xx_irq_init();
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init_i8259_irqs();
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setup_irq(GT641XX_CASCADE_IRQ, &cascade);
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setup_irq(I8259_CASCADE_IRQ, &cascade);
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}
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