threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
52 lines
2.2 KiB
C
52 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/****************************************************************************/
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/*
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* mcfpit.h -- ColdFire internal PIT timer support defines.
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*
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* (C) Copyright 2003, Greg Ungerer (gerg@snapgear.com)
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*/
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/****************************************************************************/
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#ifndef mcfpit_h
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#define mcfpit_h
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/****************************************************************************/
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/*
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* Define the PIT timer register address offsets.
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*/
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#define MCFPIT_PCSR 0x0 /* PIT control register */
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#define MCFPIT_PMR 0x2 /* PIT modulus register */
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#define MCFPIT_PCNTR 0x4 /* PIT count register */
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/*
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* Bit definitions for the PIT Control and Status register.
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*/
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#define MCFPIT_PCSR_CLK1 0x0000 /* System clock divisor */
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#define MCFPIT_PCSR_CLK2 0x0100 /* System clock divisor */
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#define MCFPIT_PCSR_CLK4 0x0200 /* System clock divisor */
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#define MCFPIT_PCSR_CLK8 0x0300 /* System clock divisor */
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#define MCFPIT_PCSR_CLK16 0x0400 /* System clock divisor */
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#define MCFPIT_PCSR_CLK32 0x0500 /* System clock divisor */
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#define MCFPIT_PCSR_CLK64 0x0600 /* System clock divisor */
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#define MCFPIT_PCSR_CLK128 0x0700 /* System clock divisor */
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#define MCFPIT_PCSR_CLK256 0x0800 /* System clock divisor */
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#define MCFPIT_PCSR_CLK512 0x0900 /* System clock divisor */
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#define MCFPIT_PCSR_CLK1024 0x0a00 /* System clock divisor */
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#define MCFPIT_PCSR_CLK2048 0x0b00 /* System clock divisor */
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#define MCFPIT_PCSR_CLK4096 0x0c00 /* System clock divisor */
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#define MCFPIT_PCSR_CLK8192 0x0d00 /* System clock divisor */
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#define MCFPIT_PCSR_CLK16384 0x0e00 /* System clock divisor */
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#define MCFPIT_PCSR_CLK32768 0x0f00 /* System clock divisor */
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#define MCFPIT_PCSR_DOZE 0x0040 /* Clock run in doze mode */
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#define MCFPIT_PCSR_HALTED 0x0020 /* Clock run in halt mode */
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#define MCFPIT_PCSR_OVW 0x0010 /* Overwrite PIT counter now */
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#define MCFPIT_PCSR_PIE 0x0008 /* Enable PIT interrupt */
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#define MCFPIT_PCSR_PIF 0x0004 /* PIT interrupt flag */
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#define MCFPIT_PCSR_RLD 0x0002 /* Reload counter */
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#define MCFPIT_PCSR_EN 0x0001 /* Enable PIT */
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#define MCFPIT_PCSR_DISABLE 0x0000 /* Disable PIT */
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/****************************************************************************/
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#endif /* mcfpit_h */
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