threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
92 lines
3.7 KiB
C
92 lines
3.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* File: m54xxgpt.h
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* Purpose: Register and bit definitions for the MCF54XX
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*
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* Notes:
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*
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*/
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#ifndef m54xxgpt_h
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#define m54xxgpt_h
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/*********************************************************************
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*
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* General Purpose Timers (GPT)
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*
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*********************************************************************/
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/* Register read/write macros */
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#define MCF_GPT_GMS0 (MCF_MBAR + 0x000800)
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#define MCF_GPT_GCIR0 (MCF_MBAR + 0x000804)
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#define MCF_GPT_GPWM0 (MCF_MBAR + 0x000808)
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#define MCF_GPT_GSR0 (MCF_MBAR + 0x00080C)
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#define MCF_GPT_GMS1 (MCF_MBAR + 0x000810)
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#define MCF_GPT_GCIR1 (MCF_MBAR + 0x000814)
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#define MCF_GPT_GPWM1 (MCF_MBAR + 0x000818)
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#define MCF_GPT_GSR1 (MCF_MBAR + 0x00081C)
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#define MCF_GPT_GMS2 (MCF_MBAR + 0x000820)
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#define MCF_GPT_GCIR2 (MCF_MBAR + 0x000824)
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#define MCF_GPT_GPWM2 (MCF_MBAR + 0x000828)
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#define MCF_GPT_GSR2 (MCF_MBAR + 0x00082C)
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#define MCF_GPT_GMS3 (MCF_MBAR + 0x000830)
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#define MCF_GPT_GCIR3 (MCF_MBAR + 0x000834)
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#define MCF_GPT_GPWM3 (MCF_MBAR + 0x000838)
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#define MCF_GPT_GSR3 (MCF_MBAR + 0x00083C)
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#define MCF_GPT_GMS(x) (MCF_MBAR + 0x000800 + ((x) * 0x010))
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#define MCF_GPT_GCIR(x) (MCF_MBAR + 0x000804 + ((x) * 0x010))
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#define MCF_GPT_GPWM(x) (MCF_MBAR + 0x000808 + ((x) * 0x010))
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#define MCF_GPT_GSR(x) (MCF_MBAR + 0x00080C + ((x) * 0x010))
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/* Bit definitions and macros for MCF_GPT_GMS */
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#define MCF_GPT_GMS_TMS(x) (((x)&0x00000007)<<0)
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#define MCF_GPT_GMS_GPIO(x) (((x)&0x00000003)<<4)
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#define MCF_GPT_GMS_IEN (0x00000100)
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#define MCF_GPT_GMS_OD (0x00000200)
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#define MCF_GPT_GMS_SC (0x00000400)
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#define MCF_GPT_GMS_CE (0x00001000)
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#define MCF_GPT_GMS_WDEN (0x00008000)
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#define MCF_GPT_GMS_ICT(x) (((x)&0x00000003)<<16)
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#define MCF_GPT_GMS_OCT(x) (((x)&0x00000003)<<20)
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#define MCF_GPT_GMS_OCPW(x) (((x)&0x000000FF)<<24)
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#define MCF_GPT_GMS_OCT_FRCLOW (0x00000000)
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#define MCF_GPT_GMS_OCT_PULSEHI (0x00100000)
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#define MCF_GPT_GMS_OCT_PULSELO (0x00200000)
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#define MCF_GPT_GMS_OCT_TOGGLE (0x00300000)
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#define MCF_GPT_GMS_ICT_ANY (0x00000000)
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#define MCF_GPT_GMS_ICT_RISE (0x00010000)
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#define MCF_GPT_GMS_ICT_FALL (0x00020000)
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#define MCF_GPT_GMS_ICT_PULSE (0x00030000)
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#define MCF_GPT_GMS_GPIO_INPUT (0x00000000)
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#define MCF_GPT_GMS_GPIO_OUTLO (0x00000020)
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#define MCF_GPT_GMS_GPIO_OUTHI (0x00000030)
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#define MCF_GPT_GMS_GPIO_MASK (0x00000030)
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#define MCF_GPT_GMS_TMS_DISABLE (0x00000000)
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#define MCF_GPT_GMS_TMS_INCAPT (0x00000001)
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#define MCF_GPT_GMS_TMS_OUTCAPT (0x00000002)
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#define MCF_GPT_GMS_TMS_PWM (0x00000003)
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#define MCF_GPT_GMS_TMS_GPIO (0x00000004)
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#define MCF_GPT_GMS_TMS_MASK (0x00000007)
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/* Bit definitions and macros for MCF_GPT_GCIR */
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#define MCF_GPT_GCIR_CNT(x) (((x)&0x0000FFFF)<<0)
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#define MCF_GPT_GCIR_PRE(x) (((x)&0x0000FFFF)<<16)
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/* Bit definitions and macros for MCF_GPT_GPWM */
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#define MCF_GPT_GPWM_LOAD (0x00000001)
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#define MCF_GPT_GPWM_PWMOP (0x00000100)
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#define MCF_GPT_GPWM_WIDTH(x) (((x)&0x0000FFFF)<<16)
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/* Bit definitions and macros for MCF_GPT_GSR */
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#define MCF_GPT_GSR_CAPT (0x00000001)
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#define MCF_GPT_GSR_COMP (0x00000002)
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#define MCF_GPT_GSR_PWMP (0x00000004)
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#define MCF_GPT_GSR_TEXP (0x00000008)
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#define MCF_GPT_GSR_PIN (0x00000100)
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#define MCF_GPT_GSR_OVF(x) (((x)&0x00000007)<<12)
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#define MCF_GPT_GSR_CAPTURE(x) (((x)&0x0000FFFF)<<16)
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/********************************************************************/
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#endif /* m54xxgpt_h */
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