threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
152 lines
3.4 KiB
C
152 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _M68K_BVME6000HW_H_
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#define _M68K_BVME6000HW_H_
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#include <asm/irq.h>
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/*
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* PIT structure
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*/
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#define BVME_PIT_BASE 0xffa00000
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typedef struct {
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unsigned char
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pad_a[3], pgcr,
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pad_b[3], psrr,
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pad_c[3], paddr,
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pad_d[3], pbddr,
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pad_e[3], pcddr,
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pad_f[3], pivr,
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pad_g[3], pacr,
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pad_h[3], pbcr,
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pad_i[3], padr,
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pad_j[3], pbdr,
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pad_k[3], paar,
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pad_l[3], pbar,
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pad_m[3], pcdr,
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pad_n[3], psr,
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pad_o[3], res1,
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pad_p[3], res2,
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pad_q[3], tcr,
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pad_r[3], tivr,
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pad_s[3], res3,
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pad_t[3], cprh,
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pad_u[3], cprm,
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pad_v[3], cprl,
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pad_w[3], res4,
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pad_x[3], crh,
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pad_y[3], crm,
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pad_z[3], crl,
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pad_A[3], tsr,
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pad_B[3], res5;
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} PitRegs_t, *PitRegsPtr;
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#define bvmepit ((*(volatile PitRegsPtr)(BVME_PIT_BASE)))
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#define BVME_RTC_BASE 0xff900000
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typedef struct {
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unsigned char
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pad_a[3], msr,
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pad_b[3], t0cr_rtmr,
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pad_c[3], t1cr_omr,
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pad_d[3], pfr_icr0,
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pad_e[3], irr_icr1,
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pad_f[3], bcd_tenms,
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pad_g[3], bcd_sec,
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pad_h[3], bcd_min,
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pad_i[3], bcd_hr,
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pad_j[3], bcd_dom,
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pad_k[3], bcd_mth,
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pad_l[3], bcd_year,
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pad_m[3], bcd_ujcc,
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pad_n[3], bcd_hjcc,
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pad_o[3], bcd_dow,
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pad_p[3], t0lsb,
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pad_q[3], t0msb,
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pad_r[3], t1lsb,
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pad_s[3], t1msb,
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pad_t[3], cmp_sec,
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pad_u[3], cmp_min,
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pad_v[3], cmp_hr,
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pad_w[3], cmp_dom,
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pad_x[3], cmp_mth,
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pad_y[3], cmp_dow,
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pad_z[3], sav_sec,
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pad_A[3], sav_min,
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pad_B[3], sav_hr,
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pad_C[3], sav_dom,
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pad_D[3], sav_mth,
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pad_E[3], ram,
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pad_F[3], test;
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} RtcRegs_t, *RtcPtr_t;
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#define BVME_I596_BASE 0xff100000
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#define BVME_ETHIRQ_REG 0xff20000b
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#define BVME_LOCAL_IRQ_STAT 0xff20000f
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#define BVME_ETHERR 0x02
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#define BVME_ABORT_STATUS 0x08
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#define BVME_NCR53C710_BASE 0xff000000
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#define BVME_SCC_A_ADDR 0xffb0000b
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#define BVME_SCC_B_ADDR 0xffb00003
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#define BVME_SCC_RTxC 7372800
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#define BVME_CONFIG_REG 0xff500003
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#define config_reg_ptr (volatile unsigned char *)BVME_CONFIG_REG
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#define BVME_CONFIG_SW1 0x08
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#define BVME_CONFIG_SW2 0x04
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#define BVME_CONFIG_SW3 0x02
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#define BVME_CONFIG_SW4 0x01
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#define BVME_IRQ_TYPE_PRIO 0
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#define BVME_IRQ_PRN (IRQ_USER+20)
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#define BVME_IRQ_TIMER (IRQ_USER+25)
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#define BVME_IRQ_I596 IRQ_AUTO_2
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#define BVME_IRQ_SCSI IRQ_AUTO_3
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#define BVME_IRQ_RTC IRQ_AUTO_6
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#define BVME_IRQ_ABORT IRQ_AUTO_7
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/* SCC interrupts */
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#define BVME_IRQ_SCC_BASE IRQ_USER
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#define BVME_IRQ_SCCB_TX IRQ_USER
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#define BVME_IRQ_SCCB_STAT (IRQ_USER+2)
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#define BVME_IRQ_SCCB_RX (IRQ_USER+4)
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#define BVME_IRQ_SCCB_SPCOND (IRQ_USER+6)
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#define BVME_IRQ_SCCA_TX (IRQ_USER+8)
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#define BVME_IRQ_SCCA_STAT (IRQ_USER+10)
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#define BVME_IRQ_SCCA_RX (IRQ_USER+12)
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#define BVME_IRQ_SCCA_SPCOND (IRQ_USER+14)
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/* Address control registers */
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#define BVME_ACR_A32VBA 0xff400003
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#define BVME_ACR_A32MSK 0xff410003
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#define BVME_ACR_A24VBA 0xff420003
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#define BVME_ACR_A24MSK 0xff430003
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#define BVME_ACR_A16VBA 0xff440003
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#define BVME_ACR_A32LBA 0xff450003
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#define BVME_ACR_A24LBA 0xff460003
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#define BVME_ACR_ADDRCTL 0xff470003
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#define bvme_acr_a32vba *(volatile unsigned char *)BVME_ACR_A32VBA
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#define bvme_acr_a32msk *(volatile unsigned char *)BVME_ACR_A32MSK
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#define bvme_acr_a24vba *(volatile unsigned char *)BVME_ACR_A24VBA
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#define bvme_acr_a24msk *(volatile unsigned char *)BVME_ACR_A24MSK
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#define bvme_acr_a16vba *(volatile unsigned char *)BVME_ACR_A16VBA
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#define bvme_acr_a32lba *(volatile unsigned char *)BVME_ACR_A32LBA
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#define bvme_acr_a24lba *(volatile unsigned char *)BVME_ACR_A24LBA
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#define bvme_acr_addrctl *(volatile unsigned char *)BVME_ACR_ADDRCTL
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#endif
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