threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
92 lines
2.9 KiB
C
92 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifdef __KERNEL__
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#ifndef _ASM_M32R_IRQ_H
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#define _ASM_M32R_IRQ_H
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#if defined(CONFIG_PLAT_USRV)
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/*
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* IRQ definitions for M32700UT
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* M32700 Chip: 64 interrupts
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* ICU of M32700UT-on-board PLD: 32 interrupts cascaded to INT1# chip pin
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*/
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#define M32700UT_NUM_CPU_IRQ (64)
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#define M32700UT_NUM_PLD_IRQ (32)
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#define M32700UT_IRQ_BASE 0
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#define M32700UT_CPU_IRQ_BASE M32700UT_IRQ_BASE
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#define M32700UT_PLD_IRQ_BASE (M32700UT_CPU_IRQ_BASE + M32700UT_NUM_CPU_IRQ)
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#define NR_IRQS (M32700UT_NUM_CPU_IRQ + M32700UT_NUM_PLD_IRQ)
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#elif defined(CONFIG_PLAT_M32700UT)
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/*
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* IRQ definitions for M32700UT(Rev.C) + M32R-LAN
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* M32700 Chip: 64 interrupts
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* ICU of M32700UT-on-board PLD: 32 interrupts cascaded to INT1# chip pin
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* ICU of M32R-LCD-on-board PLD: 32 interrupts cascaded to INT2# chip pin
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* ICU of M32R-LAN-on-board PLD: 32 interrupts cascaded to INT0# chip pin
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*/
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#define M32700UT_NUM_CPU_IRQ (64)
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#define M32700UT_NUM_PLD_IRQ (32)
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#define M32700UT_NUM_LCD_PLD_IRQ (32)
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#define M32700UT_NUM_LAN_PLD_IRQ (32)
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#define M32700UT_IRQ_BASE 0
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#define M32700UT_CPU_IRQ_BASE (M32700UT_IRQ_BASE)
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#define M32700UT_PLD_IRQ_BASE \
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(M32700UT_CPU_IRQ_BASE + M32700UT_NUM_CPU_IRQ)
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#define M32700UT_LCD_PLD_IRQ_BASE \
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(M32700UT_PLD_IRQ_BASE + M32700UT_NUM_PLD_IRQ)
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#define M32700UT_LAN_PLD_IRQ_BASE \
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(M32700UT_LCD_PLD_IRQ_BASE + M32700UT_NUM_LCD_PLD_IRQ)
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#define NR_IRQS \
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(M32700UT_NUM_CPU_IRQ + M32700UT_NUM_PLD_IRQ \
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+ M32700UT_NUM_LCD_PLD_IRQ + M32700UT_NUM_LAN_PLD_IRQ)
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#elif defined(CONFIG_PLAT_OPSPUT)
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/*
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* IRQ definitions for OPSPUT + M32R-LAN
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* OPSP Chip: 64 interrupts
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* ICU of OPSPUT-on-board PLD: 32 interrupts cascaded to INT1# chip pin
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* ICU of M32R-LCD-on-board PLD: 32 interrupts cascaded to INT2# chip pin
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* ICU of M32R-LAN-on-board PLD: 32 interrupts cascaded to INT0# chip pin
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*/
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#define OPSPUT_NUM_CPU_IRQ (64)
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#define OPSPUT_NUM_PLD_IRQ (32)
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#define OPSPUT_NUM_LCD_PLD_IRQ (32)
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#define OPSPUT_NUM_LAN_PLD_IRQ (32)
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#define OPSPUT_IRQ_BASE 0
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#define OPSPUT_CPU_IRQ_BASE (OPSPUT_IRQ_BASE)
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#define OPSPUT_PLD_IRQ_BASE \
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(OPSPUT_CPU_IRQ_BASE + OPSPUT_NUM_CPU_IRQ)
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#define OPSPUT_LCD_PLD_IRQ_BASE \
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(OPSPUT_PLD_IRQ_BASE + OPSPUT_NUM_PLD_IRQ)
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#define OPSPUT_LAN_PLD_IRQ_BASE \
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(OPSPUT_LCD_PLD_IRQ_BASE + OPSPUT_NUM_LCD_PLD_IRQ)
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#define NR_IRQS \
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(OPSPUT_NUM_CPU_IRQ + OPSPUT_NUM_PLD_IRQ \
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+ OPSPUT_NUM_LCD_PLD_IRQ + OPSPUT_NUM_LAN_PLD_IRQ)
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#elif defined(CONFIG_PLAT_M32104UT)
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/*
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* IRQ definitions for M32104UT
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* M32104 Chip: 64 interrupts
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* ICU of M32104UT-on-board PLD: 32 interrupts cascaded to INT1# chip pin
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*/
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#define M32104UT_NUM_CPU_IRQ (64)
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#define M32104UT_NUM_PLD_IRQ (32)
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#define M32104UT_IRQ_BASE 0
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#define M32104UT_CPU_IRQ_BASE M32104UT_IRQ_BASE
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#define M32104UT_PLD_IRQ_BASE (M32104UT_CPU_IRQ_BASE + M32104UT_NUM_CPU_IRQ)
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#define NR_IRQS \
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(M32104UT_NUM_CPU_IRQ + M32104UT_NUM_PLD_IRQ)
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#else
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#define NR_IRQS 64
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#endif
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#define irq_canonicalize(irq) (irq)
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#endif /* _ASM_M32R_IRQ_H */
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#endif /* __KERNEL__ */
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