threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
73 lines
2.0 KiB
C
73 lines
2.0 KiB
C
/* mach/dma.h - arch-specific DMA defines
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*
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* Copyright 2004-2008 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#ifndef _MACH_DMA_H_
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#define _MACH_DMA_H_
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#define CH_SPORT0_RX 0
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#define CH_SPORT0_TX 1
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#define CH_SPORT1_RX 2
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#define CH_SPORT1_TX 3
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#define CH_SPI0 4
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#define CH_SPI1 5
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#define CH_UART0_RX 6
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#define CH_UART0_TX 7
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#define CH_UART1_RX 8
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#define CH_UART1_TX 9
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#define CH_ATAPI_RX 10
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#define CH_ATAPI_TX 11
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#define CH_EPPI0 12
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#define CH_EPPI1 13
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#define CH_EPPI2 14
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#define CH_PIXC_IMAGE 15
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#define CH_PIXC_OVERLAY 16
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#define CH_PIXC_OUTPUT 17
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#define CH_SPORT2_RX 18
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#define CH_SPORT2_TX 19
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#define CH_SPORT3_RX 20
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#define CH_SPORT3_TX 21
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#define CH_SDH 22
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#define CH_NFC 22
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#define CH_SPI2 23
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#if defined(CONFIG_UART2_DMA_RX_ON_DMA13)
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#define CH_UART2_RX 13
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#define IRQ_UART2_RX BFIN_IRQ(37) /* UART2 RX USE EPP1 (DMA13) Interrupt */
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#define CH_UART2_TX 14
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#define IRQ_UART2_TX BFIN_IRQ(38) /* UART2 RX USE EPP1 (DMA14) Interrupt */
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#else /* Default USE SPORT2's DMA Channel */
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#define CH_UART2_RX 18
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#define IRQ_UART2_RX BFIN_IRQ(33) /* UART2 RX (DMA18) Interrupt */
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#define CH_UART2_TX 19
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#define IRQ_UART2_TX BFIN_IRQ(34) /* UART2 TX (DMA19) Interrupt */
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#endif
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#if defined(CONFIG_UART3_DMA_RX_ON_DMA15)
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#define CH_UART3_RX 15
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#define IRQ_UART3_RX BFIN_IRQ(64) /* UART3 RX USE PIXC IN0 (DMA15) Interrupt */
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#define CH_UART3_TX 16
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#define IRQ_UART3_TX BFIN_IRQ(65) /* UART3 TX USE PIXC IN1 (DMA16) Interrupt */
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#else /* Default USE SPORT3's DMA Channel */
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#define CH_UART3_RX 20
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#define IRQ_UART3_RX BFIN_IRQ(35) /* UART3 RX (DMA20) Interrupt */
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#define CH_UART3_TX 21
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#define IRQ_UART3_TX BFIN_IRQ(36) /* UART3 TX (DMA21) Interrupt */
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#endif
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#define CH_MEM_STREAM0_DEST 24
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#define CH_MEM_STREAM0_SRC 25
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#define CH_MEM_STREAM1_DEST 26
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#define CH_MEM_STREAM1_SRC 27
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#define CH_MEM_STREAM2_DEST 28
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#define CH_MEM_STREAM2_SRC 29
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#define CH_MEM_STREAM3_DEST 30
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#define CH_MEM_STREAM3_SRC 31
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#define MAX_DMA_CHANNELS 32
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#endif
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