threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
74 lines
2.9 KiB
C
74 lines
2.9 KiB
C
/*
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* Set up the interrupt priorities
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*
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* Copyright 2008 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <linux/module.h>
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#include <linux/irq.h>
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#include <asm/blackfin.h>
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void __init program_IAR(void)
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{
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/* Program the IAR0 Register with the configured priority */
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bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
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((CONFIG_IRQ_DMA0_ERROR - 7) << IRQ_DMA0_ERROR_POS) |
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((CONFIG_IRQ_PPI_ERROR - 7) << IRQ_PPI_ERROR_POS) |
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((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) |
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((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS) |
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((CONFIG_IRQ_SPI0_ERROR - 7) << IRQ_SPI0_ERROR_POS) |
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((CONFIG_IRQ_UART0_ERROR - 7) << IRQ_UART0_ERROR_POS) |
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((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS));
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bfin_write_SIC_IAR1(((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS) |
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((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
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((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
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((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) |
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((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
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((CONFIG_IRQ_SPI0 - 7) << IRQ_SPI0_POS) |
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((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
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((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS));
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bfin_write_SIC_IAR2(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
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((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) |
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((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
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((CONFIG_IRQ_PORTF_INTA - 7) << IRQ_PORTF_INTA_POS) |
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((CONFIG_IRQ_PORTF_INTB - 7) << IRQ_PORTF_INTB_POS) |
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((CONFIG_IRQ_MEM0_DMA0 - 7) << IRQ_MEM0_DMA0_POS) |
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((CONFIG_IRQ_MEM0_DMA1 - 7) << IRQ_MEM0_DMA1_POS) |
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((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS));
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bfin_write_SIC_IAR3(((CONFIG_IRQ_DMA1_ERROR - 7) << IRQ_DMA1_ERROR_POS) |
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((CONFIG_IRQ_SPORT2_ERROR - 7) << IRQ_SPORT2_ERROR_POS) |
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((CONFIG_IRQ_SPORT3_ERROR - 7) << IRQ_SPORT3_ERROR_POS) |
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((CONFIG_IRQ_SPI1_ERROR - 7) << IRQ_SPI1_ERROR_POS) |
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((CONFIG_IRQ_SPI2_ERROR - 7) << IRQ_SPI2_ERROR_POS) |
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((CONFIG_IRQ_UART1_ERROR - 7) << IRQ_UART1_ERROR_POS) |
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((CONFIG_IRQ_UART2_ERROR - 7) << IRQ_UART2_ERROR_POS));
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bfin_write_SIC_IAR4(((CONFIG_IRQ_CAN_ERROR - 7) << IRQ_CAN_ERROR_POS) |
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((CONFIG_IRQ_SPORT2_RX - 7) << IRQ_SPORT2_RX_POS) |
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((CONFIG_IRQ_SPORT2_TX - 7) << IRQ_SPORT2_TX_POS) |
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((CONFIG_IRQ_SPORT3_RX - 7) << IRQ_SPORT3_RX_POS) |
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((CONFIG_IRQ_SPORT3_TX - 7) << IRQ_SPORT3_TX_POS) |
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((CONFIG_IRQ_SPI1 - 7) << IRQ_SPI1_POS));
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bfin_write_SIC_IAR5(((CONFIG_IRQ_SPI2 - 7) << IRQ_SPI2_POS) |
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((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
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((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
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((CONFIG_IRQ_UART2_RX - 7) << IRQ_UART2_RX_POS) |
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((CONFIG_IRQ_UART2_TX - 7) << IRQ_UART2_TX_POS) |
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((CONFIG_IRQ_TWI0 - 7) << IRQ_TWI0_POS) |
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((CONFIG_IRQ_TWI1 - 7) << IRQ_TWI1_POS) |
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((CONFIG_IRQ_CAN_RX - 7) << IRQ_CAN_RX_POS));
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bfin_write_SIC_IAR6(((CONFIG_IRQ_CAN_TX - 7) << IRQ_CAN_TX_POS) |
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((CONFIG_IRQ_MEM1_DMA0 - 7) << IRQ_MEM1_DMA0_POS) |
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((CONFIG_IRQ_MEM1_DMA1 - 7) << IRQ_MEM1_DMA1_POS));
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SSYNC();
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}
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