threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
116 lines
2.6 KiB
C
116 lines
2.6 KiB
C
/*
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* arch/blackfin/kernel/reboot.c - handle shutdown/reboot
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*
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* Copyright 2004-2007 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <linux/interrupt.h>
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#include <asm/bfin-global.h>
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#include <asm/reboot.h>
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#include <asm/bfrom.h>
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/* A system soft reset makes external memory unusable so force
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* this function into L1. We use the compiler ssync here rather
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* than SSYNC() because it's safe (no interrupts and such) and
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* we save some L1. We do not need to force sanity in the SYSCR
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* register as the BMODE selection bit is cleared by the soft
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* reset while the Core B bit (on dual core parts) is cleared by
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* the core reset.
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*/
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__attribute__ ((__l1_text__, __noreturn__))
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static void bfin_reset(void)
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{
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#ifndef CONFIG_BF60x
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if (!ANOMALY_05000353 && !ANOMALY_05000386)
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bfrom_SoftReset((void *)(L1_SCRATCH_START + L1_SCRATCH_LENGTH - 20));
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/* Wait for completion of "system" events such as cache line
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* line fills so that we avoid infinite stalls later on as
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* much as possible. This code is in L1, so it won't trigger
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* any such event after this point in time.
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*/
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__builtin_bfin_ssync();
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/* Initiate System software reset. */
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bfin_write_SWRST(0x7);
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/* Due to the way reset is handled in the hardware, we need
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* to delay for 10 SCLKS. The only reliable way to do this is
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* to calculate the CCLK/SCLK ratio and multiply 10. For now,
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* we'll assume worse case which is a 1:15 ratio.
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*/
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asm(
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"LSETUP (1f, 1f) LC0 = %0\n"
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"1: nop;"
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:
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: "a" (15 * 10)
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: "LC0", "LB0", "LT0"
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);
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/* Clear System software reset */
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bfin_write_SWRST(0);
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/* The BF526 ROM will crash during reset */
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#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
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/* Seems to be fixed with newer parts though ... */
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if (__SILICON_REVISION__ < 1 && bfin_revid() < 1)
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bfin_read_SWRST();
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#endif
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/* Wait for the SWRST write to complete. Cannot rely on SSYNC
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* though as the System state is all reset now.
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*/
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asm(
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"LSETUP (1f, 1f) LC1 = %0\n"
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"1: nop;"
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:
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: "a" (15 * 1)
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: "LC1", "LB1", "LT1"
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);
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while (1)
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/* Issue core reset */
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asm("raise 1");
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#else
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while (1)
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bfin_write_RCU0_CTL(0x1);
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#endif
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}
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__attribute__((weak))
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void native_machine_restart(char *cmd)
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{
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}
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void machine_restart(char *cmd)
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{
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native_machine_restart(cmd);
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if (smp_processor_id())
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smp_call_function((void *)bfin_reset, 0, 1);
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else
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bfin_reset();
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}
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__attribute__((weak))
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void native_machine_halt(void)
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{
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idle_with_irq_disabled();
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}
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void machine_halt(void)
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{
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native_machine_halt();
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}
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__attribute__((weak))
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void native_machine_power_off(void)
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{
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idle_with_irq_disabled();
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}
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void machine_power_off(void)
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{
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native_machine_power_off();
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}
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