threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
652 lines
16 KiB
Devicetree
652 lines
16 KiB
Devicetree
/*
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* Mediatek's mt6833 SoC device tree source
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*
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* Copyright (C) 2016 MediaTek Inc.
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* Copyright (C) 2021 XiaoMi, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#ifndef CONFIG_FPGA_EARLY_PORTING
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#include <dt-bindings/pinctrl/mt6833-pinfunc.h>
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#endif
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/* chosen */
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&chosen {
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atag,videolfb-fb_base_l = <0x7e605000>;
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atag,videolfb-fb_base_h = <0x0>;
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atag,videolfb-islcmfound = <1>;
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atag,videolfb-islcm_inited = <0>;
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atag,videolfb-fps= <6000>;
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atag,videolfb-vramSize= <0x1be0000>;
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atag,videolfb-lcmname=
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"nt35595_fhd_dsi_cmd_truly_nt50358_drv";
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};
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&mt6360_pmu {
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mt6360,intr_gpio_num = <10>; /* direct defined GPIO num */
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mt6360,intr_gpio = <&pio 10 0x0>;
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};
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&mt6360_pmic {
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pwr_off_seq = [04 00 00 02];
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};
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&mt6360_typec {
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mt6360pd,intr_gpio_num = <9>; /* direct defined GPIO num */
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mt6360pd,intr_gpio = <&pio 9 0x0>;
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};
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/* AW8697 Haptic start */
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&pio {
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aw8697_reset_high: aw8697_reset_reset {
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pins_cmd_dat {
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pinmux = <PINMUX_GPIO132__FUNC_GPIO132>;
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drive-strength = <2>;
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bias-disable;
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output-high;
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};
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};
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aw8697_reset_low: aw8697_reset_active {
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pins_cmd_dat {
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pinmux = <PINMUX_GPIO132__FUNC_GPIO132>;
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drive-strength = <2>;
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bias-disable;
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output-low;
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};
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};
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aw8697_interrupt: aw8697_interrupt_active {
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pins_cmd_dat {
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pinmux = <PINMUX_GPIO6__FUNC_GPIO6>;
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drive-strength = <2>;
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bias-pull-up;
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input-enable;
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};
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};
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};
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&i2c9 {
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status = "ok"
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aw8697_haptic@5a {
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compatible = "awinic,aw8697_haptic";
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reg = <0x5A>;
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reset-gpio = <&pio 132 0>;
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irq-gpio = <&pio 6 0>;
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vib_mode = < 0 >; /*mode: RAM mode->0; CONT mode -> 1*/
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vib_f0_pre = < 1700 >;
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vib_f0_cali_percen = < 7 >;
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vib_cont_drv_lev = < 53 >;
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vib_cont_drv_lvl_ov = < 53 >;
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vib_cont_td = < 0x009A >;
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vib_cont_zc_thr = < 0x0FF1 >; /*hq 0x08F8 */
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vib_cont_num_brk = < 3 >;
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vib_f0_coeff = < 260 >; /*Don't modify it 2.604167*/
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vib_f0_trace_parameter = < 0x05 0x03 0x02 0x0f >;
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vib_bemf_config = < 0x10 0x08 0x03 0xf8 >;
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vib_sw_brake = < 0x2c >;
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vib_tset = < 0x12 >;
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vib_r_spare = < 0x68 >;
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vib_bstdbg = < 0x30 0xeb 0xd4 0 0 0 >;
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vib_effect_id_boundary = < 10 >;
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vib_effect_max = < 197 >;
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vib_trig_config = < 0 1 0 1 2
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0 1 0 1 2
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0 1 0 1 2 >;
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vib_bst_vol_default = < 0x10 >;
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vib_bst_vol_ram = < 0x11 >;
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vib_bst_vol_rtp = < 0x10 >;
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vib_rtp_time = < 20 20 20 20 20 20 20 20 20000 15000
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15000 20000 25000 15000 30000 25000 20000 20000 20000 20000
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20000 20000 20000 20000 20000 20000 20000 20000 20000 20000
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20000 20000 20000 20000 20000 20000 20000 20000 20000 20000
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20000 20000 20000 20000 20000 20000 20000 20000 20000 20000
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20000 20000 20000 20000 20000 20000 20000 20000 20000 20000
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20000 20000 20000 20000 20000 20000 20000 20000 20000 20000
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20000 20000 20000 20000 20000 20000 20000 20000 20000 20000
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20000 20000 20000 20000 20000 20000 20000 20000 20000 20000
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20000 20000 20000 20000 20000 20000 20000 20000 20000 20000
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20000 20000 20000 20000 20000 20000 20000 20000 20000 20000
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20000 20000 20000 20000 20000 20000 20000 20000 20000 20000
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20000 20000 20000 20000 20000 20000 20000 20000 20000 20000
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20000 20000 20000 20000 20000 20000 20000 20000 20000 20000
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20000 20000 20000 20000 20000 20000 20000 20000 20000 20000
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20000 20000 20000 20000 20000 20000 20000 20000 20000 20000
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20000 20000 20000 20000 20000 20000 20000 20000 20000 20000
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20000 20000 20000 20000 20000 >;
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pinctrl-names = "aw8697_reset_reset","aw8697_reset_active","aw8697_interrupt_active";
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pinctrl-0 = <&aw8697_reset_low>;
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pinctrl-1 = <&aw8697_reset_high>;
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pinctrl-2 = <&aw8697_interrupt>;
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status = "okay";
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wf_0 {
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/*CLICK*/
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mtk,effect-id = <0>;
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mtk,wf-vmax-mv = <3600>;
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mtk,wf-pattern = [3e 3e];
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mtk,wf-brake-pattern = [02 01 00 00];
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mtk,wf-play-rate-us = <20000>;
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};
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wf_1 {
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/*DOUBLE CLICK*/
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mtk,effect-id = <1>;
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mtk,wf-vmax-mv = <3600>;
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mtk,wf-pattern = [7e 3e];
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mtk,wf-brake-pattern = [03 01 00 00];
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mtk,wf-play-rate-us = <20000>;
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};
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wf_2 {
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/*TICK*/
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mtk,effect-id = <2>;
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mtk,wf-vmax-mv = <3600>;
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mtk,wf-pattern = [7e 3e];
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mtk,wf-brake-pattern = [02 01 00 00];
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mtk,wf-play-rate-us = <20000>;
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};
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wf_3 {
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/*THUD*/
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mtk,effect-id = <3>;
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mtk,wf-vmax-mv = <3600>;
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mtk,wf-pattern = [3e 3e];
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mtk,wf-brake-pattern = [02 01 00 00];
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mtk,wf-play-rate-us = <20000>;
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};
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wf_4 {
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/*POP*/
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mtk,effect-id = <4>;
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mtk,wf-vmax-mv = <3600>;
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mtk,wf-pattern = [3e 3e];
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mtk,wf-brake-pattern = [02 01 00 00];
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mtk,wf-play-rate-us = <28000>;
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};
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wf_5 {
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/*HEAVY CLICK*/
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mtk,effect-id = <5>;
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mtk,wf-vmax-mv = <3600>;
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mtk,wf-pattern = [7e 7e 7e];
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mtk,wf-brake-pattern = [03 03 01 00];
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mtk,wf-play-rate-us = <20000>;
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};
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wf_6 {
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/*id 6*/
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mtk,effect-id = <6>;
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mtk,wf-vmax-mv = <3600>;
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mtk,wf-pattern = [3e 3e];
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mtk,wf-brake-pattern = [02 01 00 00];
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mtk,wf-play-rate-us = <20000>;
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};
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wf_7 {
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/*id 7*/
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mtk,effect-id = <7>;
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mtk,wf-vmax-mv = <3600>;
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mtk,wf-pattern = [3e 3e];
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mtk,wf-brake-pattern = [02 01 00 00];
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mtk,wf-play-rate-us = <20000>;
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};
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wf_8 {
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/*id 8*/
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mtk,effect-id = <8>;
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mtk,wf-vmax-mv = <3600>;
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mtk,wf-pattern = [3e 3e];
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mtk,wf-brake-pattern = [02 01 00 00];
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mtk,wf-play-rate-us = <20000>;
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};
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wf_9 {
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/*id 9*/
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mtk,effect-id = <9>;
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mtk,wf-vmax-mv = <3600>;
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mtk,wf-pattern = [3e 3e];
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mtk,wf-brake-pattern = [02 01 00 00];
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mtk,wf-play-rate-us = <20000>;
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};
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};
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};
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/* AW8697 Haptic end */
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/* +Bug651592 caijiaqi.wt,20210607,ADD Secret battery */
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&pio {
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/* default: GPIO53, output, high */
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onewire_gpio_active: onewire_gpio_active@gpio53 {
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pins_cmd_dat {
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pinmux = <PINMUX_GPIO53__FUNC_GPIO53>;
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slew-rate = <1>;
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bias-disable;
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drive-strength = <MTK_DRIVE_4mA>;
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output-high;
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};
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};
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onewire_gpio_sleep: onewire_gpio_sleep@gpio53 {
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pins_cmd_dat {
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pinmux = <PINMUX_GPIO53__FUNC_GPIO53>;
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slew-rate = <1>;
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bias-disable;
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drive-strength = <MTK_DRIVE_4mA>;
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output-high;
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};
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};
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};
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&onewire_gpio {
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compatible = "xiaomi,onewire_gpio";
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label = "xm_onewire";
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xiaomi,version = <1>;
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xiaomi,ow_gpio = <&pio 53 0x00>;
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xiaomi,gpio_number = <53>;//
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mi,onewire-gpio-dir-addr = <0x10005010>;//
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mi,onewire-gpio-dir-set-addr = <0x10005014>;//
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mi,onewire-gpio-dir-clr-addr = <0x10005018>;//
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mi,onewire-gpio-dout-addr = <0x10005110>;//
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mi,onewire-gpio-dout-set-addr = <0x10005114>;//
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mi,onewire-gpio-dout-clr-addr = <0x10005118>;//
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mi,onewire-gpio-din-addr = <0x10005210>;//
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pinctrl-names = "onewire_active", "onewire_sleep";
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pinctrl-0 = <&onewire_gpio_active>;
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pinctrl-1 = <&onewire_gpio_sleep>;
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status = "okay";
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};
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&maxim_ds28e16 {
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compatible = "maxim,ds28e16";
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label = "max_ds28e16";
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maxim,version = <1>;
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status = "okay";
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};
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/* -Bug651592 caijiaqi.wt,20210607,ADD Secret battery */
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#ifndef CONFIG_FPGA_EARLY_PORTING
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&pio {
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mtkfb_pins_lcd_bias_enp1: lcd_bias_enp1_gpio {
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pins_cmd_dat {
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pinmux = <PINMUX_GPIO137__FUNC_GPIO137>;
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slew-rate = <1>;
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output-high;
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};
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};
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mtkfb_pins_lcd_bias_enp0: lcd_bias_enp0_gpio {
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pins_cmd_dat {
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pinmux = <PINMUX_GPIO137__FUNC_GPIO137>;
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slew-rate = <1>;
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output-low;
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};
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};
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mtkfb_pins_lcd_bias_enn1: lcd_bias_enn1_gpio {
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pins_cmd_dat {
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pinmux = <PINMUX_GPIO138__FUNC_GPIO138>;
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slew-rate = <1>;
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output-high;
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};
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};
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mtkfb_pins_lcd_bias_enn0: lcd_bias_enn0_gpio {
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pins_cmd_dat {
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pinmux = <PINMUX_GPIO138__FUNC_GPIO138>;
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slew-rate = <1>;
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output-low;
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};
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};
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mtkfb_pins_lcm_rst_out1_gpio: lcm_rst_out1_gpio {
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pins_cmd_dat {
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pinmux = <PINMUX_GPIO86__FUNC_GPIO86>;
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slew-rate = <1>;
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output-high;
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};
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};
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mtkfb_pins_lcm_rst_out0_gpio: lcm_rst_out0_gpio {
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pins_cmd_dat {
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pinmux = <PINMUX_GPIO86__FUNC_GPIO86>;
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slew-rate = <1>;
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output-low;
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};
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};
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mtkfb_pins_lcm_dsi_te: lcm_dsi_te {
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pins_cmd_dat {
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pinmux = <PINMUX_GPIO84__FUNC_DSI_TE>;
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};
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};
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};
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&mtkfb {
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pinctrl-names = "lcd_bias_enp1_gpio", "lcd_bias_enp0_gpio",
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"lcd_bias_enn1_gpio", "lcd_bias_enn0_gpio",
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"lcm_rst_out1_gpio", "lcm_rst_out0_gpio",
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"mode_te_te";
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pinctrl-0 = <&mtkfb_pins_lcd_bias_enp1>;
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pinctrl-1 = <&mtkfb_pins_lcd_bias_enp0>;
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pinctrl-2 = <&mtkfb_pins_lcd_bias_enn1>;
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pinctrl-3 = <&mtkfb_pins_lcd_bias_enn0>;
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pinctrl-4 = <&mtkfb_pins_lcm_rst_out1_gpio>;
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pinctrl-5 = <&mtkfb_pins_lcm_rst_out0_gpio>;
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pinctrl-6 = <&mtkfb_pins_lcm_dsi_te>;
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status = "okay";
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};
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&dispsys_config {
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pinctrl-names =
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"lcm_rst_out1_gpio", "lcm_rst_out0_gpio",
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"mode_te_te";
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pinctrl-0 = <&mtkfb_pins_lcm_rst_out1_gpio>;
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pinctrl-1 = <&mtkfb_pins_lcm_rst_out0_gpio>;
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pinctrl-2 = <&mtkfb_pins_lcm_dsi_te>;
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status = "okay";
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};
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&dsi0 {
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status = "okay";
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#address-cells = <1>;
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#size-cells = <0>;
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panel1: panel1@0 {
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compatible = "k16a_36_02_0a_vdo,lcm";
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reg = <0>;
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pm-enable-gpios = <&pio 136 0>;
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lcm-bl-enable-gpios = <&pio 87 0>;
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reset-gpios = <&pio 86 0>;
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bias-gpios = <&pio 137 0>,
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<&pio 138 0>;
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pinctrl-names = "default";
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lcd_dvdd-supply = <&mt_pmic_vcn13_ldo_reg>;
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port {
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panel_in1: endpoint {
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remote-endpoint = <&dsi_out>;
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};
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};
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};
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panel2: panel2@0 {
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compatible = "k16a_42_02_0b_vdo,lcm";
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reg = <1>;
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pm-enable-gpios = <&pio 136 0>;
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lcm-bl-enable-gpios = <&pio 87 0>;
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reset-gpios = <&pio 86 0>;
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bias-gpios = <&pio 137 0>,
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<&pio 138 0>;
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pinctrl-names = "default";
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lcd_dvdd-supply = <&mt_pmic_vcn13_ldo_reg>;
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port {
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panel_in2: endpoint {
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remote-endpoint = <&dsi_out>;
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};
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};
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};
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panel3: panel3@0 {
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compatible = "virtual,default,vdo";
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reg = <3>;
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pm-enable-gpios = <&pio 136 0>;
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lcm-bl-enable-gpios = <&pio 87 0>;
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reset-gpios = <&pio 86 0>;
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bias-gpios = <&pio 137 0>,
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<&pio 138 0>;
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pinctrl-names = "default";
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lcd_dvdd-supply = <&mt_pmic_vcn13_ldo_reg>;
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port {
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panel_in4: endpoint {
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remote-endpoint = <&dsi_out>;
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};
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};
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};
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ports {
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port {
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dsi_out: endpoint {
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remote-endpoint = <&panel_in1>;
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};
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};
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};
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};
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#endif
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#ifdef CONFIG_MICROTRUST_TEE_SUPPORT
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soter-shared-mem {
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compatible = "microtrust,shared_mem";
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no-map;
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#if defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT) || \
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defined(CONFIG_MTK_CAM_SECURITY_SUPPORT)
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size = <0 0x800000>;
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alignment = <0 0x1000000>;
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#else
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size = <0 0x200000>;
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alignment = <0 0x200000>;
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#endif
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alloc-ranges = <0 0x40000000 0 0x50000000>;
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};
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#endif
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#include "mediatek/cust_mt6833_touch_nt36672c_1080x2400.dtsi"
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/* accdet start */
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&accdet {
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/* accdet micbias voltage: 0x09:2.85v 0x08:2.8v 0x07,
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* 2.7v;0x05,2.5v;0x02,1.9v
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*/
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accdet-mic-vol = <8>;
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/* accdet pwm_width, pwm_thresh, fall_delay, rise_delay
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* debounce0, debounce1, debounce3, debounce4
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* eint pwm_width, eint pwm_thresh
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* eint deb(debounce0, debounce1, debounce2, debounce3), inv_debounce
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*/
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headset-mode-setting = <0x500 0x500 1 0x1f0
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0x800 0x800 0x20 0x44
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0x4 0x1
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0x5 0x3 0x3 0x5 0xe>;
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accdet-plugout-debounce = <1>;
|
|
/*1:ACC mode, 2:low cost without in bias, 6:low cost with in bias*/
|
|
accdet-mic-mode = <2>;
|
|
/*0--MD_MAX--UP_MAX--DW_MAX*/
|
|
headset-three-key-threshold = <0 80 220 400>;
|
|
headset-three-key-threshold-CDD = <0 121 192 600>;
|
|
/*0--MD_MAX--VOICE_MAX--UP_MAX--DW_MAX*/
|
|
headset-four-key-threshold = <0 58 121 192 400>;
|
|
|
|
/* select VTH to 2v and 500k, use internal resitance */
|
|
eint_use_ext_res = <0>;
|
|
status = "okay";
|
|
};
|
|
/* accdet end */
|
|
|
|
&odm {
|
|
led0:led@0 {
|
|
compatible = "mediatek,red";
|
|
led_mode = <0>;
|
|
data = <1>;
|
|
pwm_config = <0 0 0 0 0>;
|
|
};
|
|
led1:led@1 {
|
|
compatible = "mediatek,green";
|
|
led_mode = <0>;
|
|
data = <1>;
|
|
pwm_config = <0 0 0 0 0>;
|
|
};
|
|
led2:led@2 {
|
|
compatible = "mediatek,blue";
|
|
led_mode = <0>;
|
|
data = <1>;
|
|
pwm_config = <0 0 0 0 0>;
|
|
};
|
|
led3:led@3 {
|
|
compatible = "mediatek,jogball-backlight";
|
|
led_mode = <0>;
|
|
data = <1>;
|
|
pwm_config = <0 0 0 0 0>;
|
|
};
|
|
led4:led@4 {
|
|
compatible = "mediatek,keyboard-backlight";
|
|
led_mode = <0>;
|
|
data = <1>;
|
|
pwm_config = <0 0 0 0 0>;
|
|
};
|
|
led5:led@5 {
|
|
compatible = "mediatek,button-backlight";
|
|
led_mode = <0>;
|
|
data = <1>;
|
|
pwm_config = <0 0 0 0 0>;
|
|
};
|
|
led6:led@6 {
|
|
compatible = "mediatek,lcd-backlight";
|
|
led_mode = <4>;
|
|
data = <1>;
|
|
//pwm_config = <0 1 0 0 0>;
|
|
};
|
|
vibrator0:vibrator@0 {
|
|
compatible = "mediatek,vibrator";
|
|
vib_timer = <25>;
|
|
vib_limit = <9>;
|
|
vib_vol= <9>;
|
|
};
|
|
};
|
|
|
|
&i2c3 {
|
|
clock-frequency = <400000>;
|
|
mediatek,use-open-drain;
|
|
status = "okay";
|
|
st21nfc:st21nfc@8 {
|
|
compatible = "mediatek,nfc-gpio-v2";
|
|
reg = <0x08>;
|
|
gpio-rst = <92>;
|
|
gpio-rst-std = <&pio 92 0x0>;
|
|
gpio-irq = <5>;
|
|
gpio-irq-std = <&pio 5 0x0>;
|
|
status = "okay";
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
/* GPS GPIO standardization start */
|
|
&pio {
|
|
gps_pins_default: gps_default {
|
|
};
|
|
|
|
gps_l1_lna_pins_ol: gps_l1_lna@0 {
|
|
pins_cmd_dat {
|
|
pinmux = <PINMUX_GPIO140__FUNC_GPIO140>;
|
|
output-low;
|
|
};
|
|
};
|
|
gps_l1_lna_pins_dsp_ctrl: gps_l1_lna@1 {
|
|
pins_cmd_dat {
|
|
pinmux = <PINMUX_GPIO140__FUNC_GPS_L1_ELNA_EN>;
|
|
};
|
|
};
|
|
gps_l1_lna_pins_oh: gps_l1_lna@2 {
|
|
pins_cmd_dat {
|
|
pinmux = <PINMUX_GPIO140__FUNC_GPIO140>;
|
|
output-high;
|
|
};
|
|
};
|
|
|
|
gps_l5_lna_pins_ol: gps_l5_lna@0 {
|
|
pins_cmd_dat {
|
|
pinmux = <PINMUX_GPIO91__FUNC_GPIO91>;
|
|
output-low;
|
|
};
|
|
};
|
|
gps_l5_lna_pins_dsp_ctrl: gps_l5_lna@1 {
|
|
pins_cmd_dat {
|
|
pinmux = <PINMUX_GPIO91__FUNC_GPS_L5_ELNA_EN>;
|
|
};
|
|
};
|
|
gps_l5_lna_pins_oh: gps_l5_lna@2 {
|
|
pins_cmd_dat {
|
|
pinmux = <PINMUX_GPIO91__FUNC_GPIO91>;
|
|
output-high;
|
|
};
|
|
};
|
|
};
|
|
|
|
&gps {
|
|
pinctrl-names = "default",
|
|
"gps_l1_lna_disable",
|
|
"gps_l1_lna_dsp_ctrl",
|
|
"gps_l1_lna_enable",
|
|
"gps_l5_lna_disable",
|
|
"gps_l5_lna_dsp_ctrl",
|
|
"gps_l5_lna_enable";
|
|
pinctrl-0 = <&gps_pins_default>;
|
|
pinctrl-1 = <&gps_l1_lna_pins_ol>;
|
|
pinctrl-2 = <&gps_l1_lna_pins_dsp_ctrl>;
|
|
pinctrl-3 = <&gps_l1_lna_pins_oh>;
|
|
pinctrl-4 = <&gps_l5_lna_pins_ol>;
|
|
pinctrl-5 = <&gps_l5_lna_pins_dsp_ctrl>;
|
|
pinctrl-6 = <&gps_l5_lna_pins_oh>;
|
|
status = "okay";
|
|
};
|
|
|
|
&pio {
|
|
fpsensor_fpc_rst_low: fpsensor_fpc_rst_low {
|
|
pins_cmd_dat {
|
|
pinmux = <PINMUX_GPIO17__FUNC_GPIO17>;
|
|
slew-rate = <1>;
|
|
output-low;
|
|
};
|
|
};
|
|
|
|
fpsensor_fpc_rst_high: fpsensor_fpc_rst_high {
|
|
pins_cmd_dat {
|
|
pinmux = <PINMUX_GPIO17__FUNC_GPIO17>;
|
|
slew-rate = <1>;
|
|
output-high;
|
|
};
|
|
};
|
|
};
|
|
&pio {
|
|
fpsensor_goodix_rst_low: fpsensor_goodix_rst_low {
|
|
pins_cmd_dat {
|
|
pinmux = <PINMUX_GPIO17__FUNC_GPIO17>;
|
|
slew-rate = <1>;
|
|
output-low;
|
|
};
|
|
};
|
|
|
|
fpsensor_goodix_rst_high: fpsensor_goodix_rst_high {
|
|
pins_cmd_dat {
|
|
pinmux = <PINMUX_GPIO17__FUNC_GPIO17>;
|
|
slew-rate = <1>;
|
|
output-high;
|
|
};
|
|
};
|
|
};
|
|
&spi5 {
|
|
fpc_spi@0 {
|
|
compatible = "fpc,fpc_spi";
|
|
reg = <0>;
|
|
fpc,enable-wakeup;
|
|
spi-max-frequency = <10000000>;
|
|
netlink-event = <31>;
|
|
vfp-supply = <&mt_pmic_vfp_ldo_reg>;
|
|
pinctrl-names = "fpsensor_fpc_rst_low", "fpsensor_fpc_rst_high";
|
|
pinctrl-0 = <&fpsensor_fpc_rst_low>;
|
|
pinctrl-1 = <&fpsensor_fpc_rst_high>;
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
&fpsensor_fp_eint {
|
|
interrupt-parent = <&pio>;
|
|
interrupts = <18 IRQ_TYPE_EDGE_RISING 18 0>;
|
|
int-gpios = <&pio 18 0>;
|
|
pinctrl-names = "fpsensor_goodix_rst_low", "fpsensor_goodix_rst_high";
|
|
pinctrl-0 = <&fpsensor_goodix_rst_low>;
|
|
pinctrl-1 = <&fpsensor_goodix_rst_high>;
|
|
status = "okay";
|
|
};
|
|
/* GPS GPIO standardization end */
|
|
// #include "mediatek/cust_mt6833_camera.dtsi"
|
|
#include "mediatek/cust_evergo_camera.dtsi"
|
|
#include "mediatek/evergo/cust.dtsi"
|
|
#include "mediatek/sia81xx.dtsi"
|
|
#include "mediatek/sc8551.dtsi"
|
|
#include "mediatek/ln8000.dtsi"
|
|
#include "mediatek/irtx_led.dtsi"
|
|
|
|
/*End of this file, DO NOT ADD ANYTHING HERE*/
|