threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
49 lines
1.6 KiB
C
49 lines
1.6 KiB
C
/* arch/arm/plat-samsung/include/plat/regs-spi.h
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*
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* Copyright (c) 2004 Fetron GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* S3C2410 SPI register definition
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*/
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#ifndef __ASM_ARCH_REGS_SPI_H
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#define __ASM_ARCH_REGS_SPI_H
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#define S3C2410_SPI1 (0x20)
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#define S3C2412_SPI1 (0x100)
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#define S3C2410_SPCON (0x00)
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#define S3C2410_SPCON_SMOD_DMA (2 << 5) /* DMA mode */
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#define S3C2410_SPCON_SMOD_INT (1 << 5) /* interrupt mode */
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#define S3C2410_SPCON_SMOD_POLL (0 << 5) /* polling mode */
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#define S3C2410_SPCON_ENSCK (1 << 4) /* Enable SCK */
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#define S3C2410_SPCON_MSTR (1 << 3) /* Master:1, Slave:0 select */
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#define S3C2410_SPCON_CPOL_HIGH (1 << 2) /* Clock polarity select */
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#define S3C2410_SPCON_CPOL_LOW (0 << 2) /* Clock polarity select */
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#define S3C2410_SPCON_CPHA_FMTB (1 << 1) /* Clock Phase Select */
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#define S3C2410_SPCON_CPHA_FMTA (0 << 1) /* Clock Phase Select */
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#define S3C2410_SPSTA (0x04)
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#define S3C2410_SPSTA_DCOL (1 << 2) /* Data Collision Error */
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#define S3C2410_SPSTA_MULD (1 << 1) /* Multi Master Error */
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#define S3C2410_SPSTA_READY (1 << 0) /* Data Tx/Rx ready */
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#define S3C2412_SPSTA_READY_ORG (1 << 3)
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#define S3C2410_SPPIN (0x08)
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#define S3C2410_SPPIN_ENMUL (1 << 2) /* Multi Master Error detect */
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#define S3C2410_SPPIN_RESERVED (1 << 1)
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#define S3C2410_SPPIN_KEEP (1 << 0) /* Master Out keep */
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#define S3C2410_SPPRE (0x0C)
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#define S3C2410_SPTDAT (0x10)
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#define S3C2410_SPRDAT (0x14)
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#endif /* __ASM_ARCH_REGS_SPI_H */
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