threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
95 lines
2.5 KiB
C
95 lines
2.5 KiB
C
/*
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* R8A7740 processor support
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*
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* Copyright (C) 2011 Renesas Solutions Corp.
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* Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/arm-gic.h>
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#include <asm/mach/map.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/time.h>
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#include "common.h"
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/*
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* r8a7740 chip has lasting errata on MERAM buffer.
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* this is work-around for it.
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* see
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* "Media RAM (MERAM)" on r8a7740 documentation
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*/
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#define MEBUFCNTR 0xFE950098
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static void __init r8a7740_meram_workaround(void)
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{
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void __iomem *reg;
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reg = ioremap_nocache(MEBUFCNTR, 4);
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if (reg) {
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iowrite32(0x01600164, reg);
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iounmap(reg);
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}
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}
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static void __init r8a7740_init_irq_of(void)
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{
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void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10);
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void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10);
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void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4);
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irqchip_init();
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/* route signals to GIC */
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iowrite32(0x0, pfc_inta_ctrl);
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/*
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* To mask the shared interrupt to SPI 149 we must ensure to set
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* PRIO *and* MASK. Else we run into IRQ floods when registering
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* the intc_irqpin devices
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*/
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iowrite32(0x0, intc_prio_base + 0x0);
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iowrite32(0x0, intc_prio_base + 0x4);
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iowrite32(0x0, intc_prio_base + 0x8);
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iowrite32(0x0, intc_prio_base + 0xc);
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iowrite8(0xff, intc_msk_base + 0x0);
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iowrite8(0xff, intc_msk_base + 0x4);
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iowrite8(0xff, intc_msk_base + 0x8);
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iowrite8(0xff, intc_msk_base + 0xc);
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iounmap(intc_prio_base);
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iounmap(intc_msk_base);
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iounmap(pfc_inta_ctrl);
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}
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static void __init r8a7740_generic_init(void)
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{
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r8a7740_meram_workaround();
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}
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static const char *const r8a7740_boards_compat_dt[] __initconst = {
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"renesas,r8a7740",
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NULL,
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};
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DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
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.l2c_aux_val = 0,
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.l2c_aux_mask = ~0,
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.init_early = shmobile_init_delay,
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.init_irq = r8a7740_init_irq_of,
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.init_machine = r8a7740_generic_init,
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.init_late = shmobile_init_late,
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.dt_compat = r8a7740_boards_compat_dt,
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MACHINE_END
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