threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
68 lines
1.7 KiB
Devicetree
68 lines
1.7 KiB
Devicetree
/*
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* Copyright (C) 2019 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
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*/
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&i2c7 {
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#address-cells = <1>;
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#size-cells = <0>;
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rt-swchg@53 {
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compatible = "richtek,swchg";
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reg = <0x53>;
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status = "okay";
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rt,intr_gpio = <&pio 42 0x0>; /* GPIO */
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rt,intr_gpio_num = <42>; /* direct defined GPIO num */
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/*
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* rt,ceb_gpio = <&pio 43 0x0>;
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* rt,ceb_gpio_num = <43>;
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*/
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rt9471 {
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/*
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* Charger name
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* Primary charger: primary_chg
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* Secondary charger: secondary_chg
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*/
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chg_name = "primary_chg";
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chg_alias_name = "rt9471_chg";
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rm-dev-addr = /bits/ 8 <0x53>;
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rm-name = "rt9471";
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interrupt-names = "wdt", "chg_mivr", "vbus_gd",
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"bc12_done", "detach", "vac_ov",
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"otg_fault", "chg_rdy", "chg_done",
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"aicc_done", "pe_done", "chg_tout",
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"rechg", "chg_batov";
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vac_ovp = <14000000>; /* uV */
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mivr = <4400000>; /* uV */
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aicr = <500000>; /* uA */
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cv = <4350000>; /* uV */
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ichg = <1000000>; /* uA */
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ieoc = <200000>; /* uA */
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safe_tmr = <10>; /* hour */
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wdt = <40>; /* sec */
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/*
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* 0: MIVR register
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* 1: MIVR = VBAT + 200mV
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* 2: MIVR = VBAT + 250mV
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* >= 3: MIVR = VBAT + 300mV
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*/
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mivr_track = <0>;
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en_safe_tmr;
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en_te;
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/* en_jeita; */
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/* ceb_invert; */
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/* dis_i2c_tout; */
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en_qon_rst;
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/* auto_aicr; */
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};
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};
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};
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