threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
50 lines
1.0 KiB
Devicetree
50 lines
1.0 KiB
Devicetree
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include "dm814x-clocks.dtsi"
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/* Compared to dm814x, dra62x does not have hdic, l3 or dss PLLs */
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&adpll_hdvic_ck {
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status = "disabled";
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};
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&adpll_l3_ck {
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status = "disabled";
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};
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&adpll_dss_ck {
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status = "disabled";
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};
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/* Compared to dm814x, dra62x has interconnect clocks on isp PLL */
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&sysclk4_ck {
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clocks = <&adpll_isp_ck 1>;
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};
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&sysclk5_ck {
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clocks = <&adpll_isp_ck 1>;
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};
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&sysclk6_ck {
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clocks = <&adpll_isp_ck 1>;
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};
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/*
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* Compared to dm814x, dra62x has different shifts and more mux options.
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* Please add the extra options for ysclk_14 and 16 if really needed.
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*/
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&timer1_fck {
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clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
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&aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
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ti,bit-shift = <4>;
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};
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&timer2_fck {
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clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
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&aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
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ti,bit-shift = <8>;
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};
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