threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
45 lines
1.3 KiB
Plaintext
45 lines
1.3 KiB
Plaintext
Allwinner A31/H3 SPI controller
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Required properties:
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- compatible: Should be "allwinner,sun6i-a31-spi" or "allwinner,sun8i-h3-spi".
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- reg: Should contain register location and length.
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- interrupts: Should contain interrupt.
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- clocks: phandle to the clocks feeding the SPI controller. Two are
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needed:
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- "ahb": the gated AHB parent clock
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- "mod": the parent module clock
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- clock-names: Must contain the clock names described just above
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- resets: phandle to the reset controller asserting this device in
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reset
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Optional properties:
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- dmas: DMA specifiers for rx and tx dma. See the DMA client binding,
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Documentation/devicetree/bindings/dma/dma.txt
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- dma-names: DMA request names should include "rx" and "tx" if present.
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Example:
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spi1: spi@01c69000 {
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compatible = "allwinner,sun6i-a31-spi";
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reg = <0x01c69000 0x1000>;
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interrupts = <0 66 4>;
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clocks = <&ahb1_gates 21>, <&spi1_clk>;
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clock-names = "ahb", "mod";
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resets = <&ahb1_rst 21>;
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};
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spi0: spi@01c68000 {
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compatible = "allwinner,sun8i-h3-spi";
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reg = <0x01c68000 0x1000>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
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clock-names = "ahb", "mod";
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dmas = <&dma 23>, <&dma 23>;
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dma-names = "rx", "tx";
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pinctrl-names = "default";
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pinctrl-0 = <&spi0_pins>;
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resets = <&ccu RST_BUS_SPI0>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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