threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
44 lines
1.2 KiB
Plaintext
44 lines
1.2 KiB
Plaintext
Hisilicon System Reset Controller
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======================================
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Please also refer to reset.txt in this directory for common reset
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controller binding usage.
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The reset controller registers are part of the system-ctl block on
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hi3660 SoC.
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Required properties:
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- compatible: should be
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"hisilicon,hi3660-reset"
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- hisi,rst-syscon: phandle of the reset's syscon.
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- #reset-cells : Specifies the number of cells needed to encode a
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reset source. The type shall be a <u32> and the value shall be 2.
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Cell #1 : offset of the reset assert control
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register from the syscon register base
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offset + 4: deassert control register
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offset + 8: status control register
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Cell #2 : bit position of the reset in the reset control register
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Example:
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iomcu: iomcu@ffd7e000 {
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compatible = "hisilicon,hi3660-iomcu", "syscon";
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reg = <0x0 0xffd7e000 0x0 0x1000>;
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};
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iomcu_rst: iomcu_rst_controller {
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compatible = "hisilicon,hi3660-reset";
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hisi,rst-syscon = <&iomcu>;
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#reset-cells = <2>;
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};
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Specifying reset lines connected to IP modules
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==============================================
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example:
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i2c0: i2c@..... {
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...
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resets = <&iomcu_rst 0x20 3>; /* offset: 0x20; bit: 3 */
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...
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};
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