threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
38 lines
1.1 KiB
Plaintext
38 lines
1.1 KiB
Plaintext
Qualcomm DWC3 HS AND SS PHY CONTROLLER
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--------------------------------------
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DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer
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controllers. Each DWC3 PHY controller should have its own node.
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Required properties:
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- compatible: should contain one of the following:
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- "qcom,dwc3-hs-usb-phy" for High Speed Synopsis PHY controller
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- "qcom,dwc3-ss-usb-phy" for Super Speed Synopsis PHY controller
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- reg: offset and length of the DWC3 PHY controller register set
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- #phy-cells: must be zero
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- clocks: a list of phandles and clock-specifier pairs, one for each entry in
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clock-names.
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- clock-names: Should contain "ref" for the PHY reference clock
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Optional clocks:
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"xo" External reference clock
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Example:
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phy@100f8800 {
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compatible = "qcom,dwc3-hs-usb-phy";
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reg = <0x100f8800 0x30>;
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clocks = <&gcc USB30_0_UTMI_CLK>;
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clock-names = "ref";
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#phy-cells = <0>;
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};
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phy@100f8830 {
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compatible = "qcom,dwc3-ss-usb-phy";
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reg = <0x100f8830 0x30>;
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clocks = <&gcc USB30_0_MASTER_CLK>;
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clock-names = "ref";
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#phy-cells = <0>;
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};
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