threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
41 lines
1.3 KiB
Plaintext
41 lines
1.3 KiB
Plaintext
Lantiq XWAY SoC RCU USB 1.1/2.0 PHY binding
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===========================================
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This binding describes the USB PHY hardware provided by the RCU module on the
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Lantiq XWAY SoCs.
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This node has to be a sub node of the Lantiq RCU block.
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-------------------------------------------------------------------------------
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Required properties (controller (parent) node):
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- compatible : Should be one of
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"lantiq,ase-usb2-phy"
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"lantiq,danube-usb2-phy"
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"lantiq,xrx100-usb2-phy"
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"lantiq,xrx200-usb2-phy"
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"lantiq,xrx300-usb2-phy"
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- reg : Defines the following sets of registers in the parent
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syscon device
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- Offset of the USB PHY configuration register
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- Offset of the USB Analog configuration
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register (only for xrx200 and xrx200)
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- clocks : References to the (PMU) "phy" clk gate.
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- clock-names : Must be "phy"
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- resets : References to the RCU USB configuration reset bits.
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- reset-names : Must be one of the following:
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"phy" (optional)
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"ctrl" (shared)
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-------------------------------------------------------------------------------
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Example for the USB PHYs on an xRX200 SoC:
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usb_phy0: usb2-phy@18 {
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compatible = "lantiq,xrx200-usb2-phy";
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reg = <0x18 4>, <0x38 4>;
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clocks = <&pmu PMU_GATE_USB0_PHY>;
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clock-names = "phy";
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resets = <&reset1 4 4>, <&reset0 4 4>;
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reset-names = "phy", "ctrl";
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#phy-cells = <0>;
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};
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