threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
45 lines
1.4 KiB
Plaintext
45 lines
1.4 KiB
Plaintext
Xilinx Axi CAN/Zynq CANPS controller Device Tree Bindings
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---------------------------------------------------------
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Required properties:
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- compatible : Should be "xlnx,zynq-can-1.0" for Zynq CAN
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controllers and "xlnx,axi-can-1.00.a" for Axi CAN
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controllers.
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- reg : Physical base address and size of the Axi CAN/Zynq
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CANPS registers map.
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- interrupts : Property with a value describing the interrupt
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number.
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- interrupt-parent : Must be core interrupt controller
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- clock-names : List of input clock names - "can_clk", "pclk"
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(For CANPS), "can_clk" , "s_axi_aclk"(For AXI CAN)
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(See clock bindings for details).
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- clocks : Clock phandles (see clock bindings for details).
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- tx-fifo-depth : Can Tx fifo depth.
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- rx-fifo-depth : Can Rx fifo depth.
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Example:
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For Zynq CANPS Dts file:
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zynq_can_0: can@e0008000 {
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compatible = "xlnx,zynq-can-1.0";
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clocks = <&clkc 19>, <&clkc 36>;
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clock-names = "can_clk", "pclk";
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reg = <0xe0008000 0x1000>;
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interrupts = <0 28 4>;
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interrupt-parent = <&intc>;
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tx-fifo-depth = <0x40>;
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rx-fifo-depth = <0x40>;
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};
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For Axi CAN Dts file:
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axi_can_0: axi-can@40000000 {
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compatible = "xlnx,axi-can-1.00.a";
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clocks = <&clkc 0>, <&clkc 1>;
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clock-names = "can_clk","s_axi_aclk" ;
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reg = <0x40000000 0x10000>;
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interrupt-parent = <&intc>;
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interrupts = <0 59 1>;
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tx-fifo-depth = <0x40>;
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rx-fifo-depth = <0x40>;
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};
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