threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
49 lines
2.0 KiB
Plaintext
49 lines
2.0 KiB
Plaintext
SMI (Smart Multimedia Interface) Common
|
|
|
|
The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
|
|
|
|
Mediatek SMI have two generations of HW architecture, here is the list
|
|
which generation the Socs use:
|
|
generation 1: mt2701.
|
|
generation 2: mt2712, mt8173 and mt8183.
|
|
|
|
There's slight differences between the two SMI, for generation 2, the
|
|
register which control the iommu port is at each larb's register base. But
|
|
for generation 1, the register is at smi ao base(smi always on register
|
|
base). Besides that, the smi async clock should be prepared and enabled for
|
|
SMI generation 1 to transform the smi clock into emi clock domain, but that is
|
|
not needed for SMI generation 2.
|
|
|
|
Required properties:
|
|
- compatible : must be one of :
|
|
"mediatek,mt2701-smi-common"
|
|
"mediatek,mt2712-smi-common"
|
|
"mediatek,mt8173-smi-common"
|
|
"mediatek,mt8183-smi-common"
|
|
- reg : the register and size of the SMI block.
|
|
- power-domains : a phandle to the power domain of this local arbiter.
|
|
- clocks : Must contain an entry for each entry in clock-names.
|
|
- clock-names : must contain 3 entries for generation 1 smi HW and 2 entries
|
|
for generation 2 smi HW as follows:
|
|
- "apb" : Advanced Peripheral Bus clock, It's the clock for setting
|
|
the register.
|
|
- "smi" : It's the clock for transfer data and command.
|
|
They may be the same if both source clocks are the same.
|
|
- "async" : asynchronous clock, it help transform the smi clock into the emi
|
|
clock domain, this clock is only needed by generation 1 smi HW.
|
|
and these 2 option clocks for generation 2 smi HW:
|
|
- "gals0": the path0 clock of GALS(Global Async Local Sync).
|
|
- "gals1": the path1 clock of GALS(Global Async Local Sync).
|
|
Note that "gals0" and "gals1" clock only exist while the SMI HW has "GALS"
|
|
modules.
|
|
|
|
Example:
|
|
smi_common: smi@14022000 {
|
|
compatible = "mediatek,mt8173-smi-common";
|
|
reg = <0 0x14022000 0 0x1000>;
|
|
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
|
clocks = <&mmsys CLK_MM_SMI_COMMON>,
|
|
<&mmsys CLK_MM_SMI_COMMON>;
|
|
clock-names = "apb", "smi";
|
|
};
|