threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
33 lines
1.2 KiB
Plaintext
33 lines
1.2 KiB
Plaintext
Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
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Synopsys DesignWare provides interrupt controller IP for APB known as
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dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with
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APB bus, e.g. Marvell Armada 1500.
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Required properties:
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- compatible: shall be "snps,dw-apb-ictl"
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- reg: physical base address of the controller and length of memory mapped
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region starting with ENABLE_LOW register
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- interrupt-controller: identifies the node as an interrupt controller
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- #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1
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- interrupts: interrupt reference to primary interrupt controller
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- interrupt-parent: (optional) reference specific primary interrupt controller
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The interrupt sources map to the corresponding bits in the interrupt
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registers, i.e.
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- 0 maps to bit 0 of low interrupts,
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- 1 maps to bit 1 of low interrupts,
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- 32 maps to bit 0 of high interrupts,
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- 33 maps to bit 1 of high interrupts,
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- (optional) fast interrupts start at 64.
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Example:
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aic: interrupt-controller@3000 {
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compatible = "snps,dw-apb-ictl";
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reg = <0x3000 0xc00>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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};
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