threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
47 lines
1.4 KiB
Plaintext
47 lines
1.4 KiB
Plaintext
Binding for Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller
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The MISC interrupt controller is a secondary controller for lower priority
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interrupt.
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Required Properties:
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- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc" or
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"qca,<soctype>-cpu-intc", "qca,ar7240-misc-intc"
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- reg: Base address and size of the controllers memory area
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- interrupt-parent: phandle of the parent interrupt controller.
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- interrupts: Interrupt specifier for the controllers interrupt.
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- interrupt-controller : Identifies the node as an interrupt controller
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- #interrupt-cells : Specifies the number of cells needed to encode interrupt
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source, should be 1
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Compatible fallback depends on the SoC. Use ar7100 for ar71xx and ar913x,
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use ar7240 for all other SoCs.
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Please refer to interrupts.txt in this directory for details of the common
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Interrupt Controllers bindings used by client devices.
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Example:
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interrupt-controller@18060010 {
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compatible = "qca,ar9132-misc-intc", "qca,ar7100-misc-intc";
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reg = <0x18060010 0x4>;
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interrupt-parent = <&cpuintc>;
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interrupts = <6>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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Another example:
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interrupt-controller@18060010 {
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compatible = "qca,ar9331-misc-intc", qca,ar7240-misc-intc";
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reg = <0x18060010 0x4>;
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interrupt-parent = <&cpuintc>;
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interrupts = <6>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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