threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
42 lines
1.4 KiB
Plaintext
42 lines
1.4 KiB
Plaintext
Broadcom BCM3380-style Level 1 / Level 2 interrupt controller
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This interrupt controller shows up in various forms on many BCM338x/BCM63xx
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chipsets. It has the following properties:
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- outputs a single interrupt signal to its interrupt controller parent
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- contains one or more enable/status word pairs, which often appear at
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different offsets in different blocks
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- no atomic set/clear operations
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Required properties:
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- compatible: should be "brcm,bcm3380-l2-intc"
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- reg: specifies one or more enable/status pairs, in the following format:
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<enable_reg 0x4 status_reg 0x4>...
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- interrupt-controller: identifies the node as an interrupt controller
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- #interrupt-cells: specifies the number of cells needed to encode an interrupt
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source, should be 1.
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- interrupt-parent: specifies the phandle to the parent interrupt controller
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this one is cascaded from
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- interrupts: specifies the interrupt line in the interrupt-parent controller
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node, valid values depend on the type of parent interrupt controller
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Optional properties:
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- brcm,irq-can-wake: if present, this means the L2 controller can be used as a
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wakeup source for system suspend/resume.
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Example:
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irq0_intc: interrupt-controller@10000020 {
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compatible = "brcm,bcm3380-l2-intc";
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reg = <0x10000024 0x4 0x1000002c 0x4>,
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<0x10000020 0x4 0x10000028 0x4>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&cpu_intc>;
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interrupts = <2>;
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};
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