threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
37 lines
1.3 KiB
Plaintext
37 lines
1.3 KiB
Plaintext
* Amlogic Meson SAR (Successive Approximation Register) A/D converter
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Required properties:
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- compatible: depending on the SoC this should be one of:
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- "amlogic,meson8-saradc" for Meson8
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- "amlogic,meson8b-saradc" for Meson8b
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- "amlogic,meson-gxbb-saradc" for GXBB
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- "amlogic,meson-gxl-saradc" for GXL
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- "amlogic,meson-gxm-saradc" for GXM
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along with the generic "amlogic,meson-saradc"
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- reg: the physical base address and length of the registers
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- interrupts: the interrupt indicating end of sampling
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- clocks: phandle and clock identifier (see clock-names)
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- clock-names: mandatory clocks:
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- "clkin" for the reference clock (typically XTAL)
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- "core" for the SAR ADC core clock
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optional clocks:
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- "sana" for the analog clock
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- "adc_clk" for the ADC (sampling) clock
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- "adc_sel" for the ADC (sampling) clock mux
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- vref-supply: the regulator supply for the ADC reference voltage
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- #io-channel-cells: must be 1, see ../iio-bindings.txt
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Example:
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saradc: adc@8680 {
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compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
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#io-channel-cells = <1>;
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reg = <0x0 0x8680 0x0 0x34>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
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clocks = <&xtal>,
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<&clkc CLKID_SAR_ADC>,
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<&clkc CLKID_SANA>,
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<&clkc CLKID_SAR_ADC_CLK>,
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<&clkc CLKID_SAR_ADC_SEL>;
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clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
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};
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